• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.554-557
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• 2002

In this paper, PDP driving circuit is designed to show the pattern of still-image with ADS (Address Display Separation) driving method. The designed circuits consist of three stages which are the image processing program, digital logic parts, and power circuits. The Image processing program is designed serial-communication with RS-232C using BASIC language. Digital logic parts design ADS driving signals with Xilinx FPGA and are simulated by ModelSim 5.5f. Power circuits convert output of digital logic parts into high voltage which panel is drived.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.793-794
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• 2011

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.398-399
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• 2019

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.

• The Journal of Korean Association of Computer Education
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• v.11 no.1
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• pp.23-32
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• 2008

In this paper, we have investigated the education effect of a web-based virtual laboratory for digital logic circuits which consists of multimedia contents about the usages of equipments for logic circuit experiments and the experimental logic circuits. In case of the engineering experiment of the lower grades in universities, preunderstanding about the usages of experimental equipments and the experimental circuits is necessary for the learners to conduct the experiments well. But it is impossible for the learners to have access to the real experimental equipments earlier due to the lack of equipments and the difficulty in management of the equipments. We have implemented the digital logic circuit virtual laboratory which provides the same experimental environment as a real experimental lab, and the learner can conduct the same experiments as the real ones before the real laboratory class. The learners using the laboratory have reduced the experiment completion time by the average of about 8.2% during a term, compared with the learners not using the lab.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.6
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• pp.558-563
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• 2005

In this paper, we implemented a web-based virtual laboratory system(VLab system) with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since the proposed VLab system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, the VLab system is designed to increase the learning and teaching efficiencies of both the learners and the educators, respectively. The learners will be able to achieve high teaming standard and the educators save their time and labor. The virtual experiments on our VLab system are performed according to the following procedure: (1) Circuit composition on the virtual bread board (2). Applying input voltage (3) Output measurements (4) Checkout of experiment results. Furthermore, the circuit composition on the virtual bread board and its corresponding online schematic diagram are displayed together on the VLab system for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.535-538
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• 2005

We report the influence of the threshold voltage and mobility fluctuation in TFT on current mode digital circuit performance. We found that the threshold voltage showed more serious circuit malfunction. We studied new circuit configuration for improvement.

• Progress in Superconductivity
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• v.6 no.1
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.