• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1784-1787
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• 2002

Two-dimensional (2-D) digital filters are widely useful inn image processing and other 2-D digital signal processing fields, but designing 2-D filters is much more difficult than designing one-dimensional (1-D) ones. This paper provides a new insight into the existing singular value decomposition (SVD)-based design approach in the sense that the SVD-based design can be performed more efficiently by exploiting the symmetries of the given 2-D magnitude specifications. By using the specification symmetries. only half of the 1-D filters (sub-filters) need to be designed. which significantly simplifies the design process and reduces the computer storage required for 1-D sub-filter coefficients. Another novel point of this paper si that an objective criterion is proposed for selecting appropriate sub-filter orders in order to reduce the hardware implementation cost. A design example is given to illustrate the effectiveness of the SVD-based design approach by exploiting specification symmetry and new order-selecting criterion.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.113-118
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• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2513-2515
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• 2005

Recently genetic algorithm techniques have widely used in adaptive and control schemes for production systems. However, generally it costs a lot of time for leaming in the case applied in control system. Furthermore, the physical meaning of genetic algorithm constructed as a result is not obvious. And this method has been used as a learning algorithm to estimate the parameter of a genetic algorithm used for identification of the process dynamics of Butter-Worth analog filter and it was shown that this method offered superior capability over the genetic algorithm. A genetic algorithm is used to solve the parameter identification problem for linear and nonlinear digital filters. This paper goal estimate Butter-Worth analog filter parameter using the genetic algorithm.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3066-3068
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• 2005

Noise can make surrounding environments inferior and deteriorates operation efficiency, and it can bring aural damage as well as give a person psychological stress. Therefore, necessity of study about noise control is increased for better labor conditions and agreeable habitat. In this paper, implementation of active mufflers using a stable IIR adaptive filters is presented. The IIR filter structure is more effective when acoustic feedback exists, but the adaptive IIR filters could be unstable when the filter algorithm is not yet converged. A stabilizing process for adaptive IIR filter is introduced in this paper. Experiments using a TMS320C32 digital signal processor have performed to show the effectiveness of a proposed algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1532-1539
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digial loop filter is combined with an error symbol detecting circuit using an adaptive window. Suppressing the tracking process when hop mute and impulse noises are detected improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. The simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.477-483
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• 1986

This paper studies the design of a CMOS operational amplifier for the switched capacitor filter by computer simulation, and presents the results of measurement. The operational amplifier composed of two stages is fabricated in the CMOS digital process. The DC voltage gain of the operational amplifier is 66dB, and the unity gain bandwidth is 833kHz. These results satisfy the performance requirmance requirements for the operational amplifier of the switched capacitor filter.

• Journal of the Korean institute of surface engineering
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• v.42 no.5
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• pp.216-219
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• 2009

A surface acoustic wave (SAW) filter structure was fabricated employing $4{\mu}m$ thick nanocrystalline diamond (NCD) and $2.2{\mu}m$ thick ZnO films on Si wafer. The NCD film was deposited in an $Ar/CH_4$ gas mixture by microwave plasma chemical vapor deposition method. The ZnO film was formed over the NCD film in an RF magnetron sputter using ZnO target and $Ar/O_2$ gas. On the top of the two layers, copper film was deposited by the RF sputter and inter digital transducer (IDT) electrode pattern (line/space : $1.5/1.5{\mu}m$) was defined by the photolithography including a lift-off etching process. The fabricated SAW filter exhibited the center frequency of 1.66 GHz and the phase velocity of 9,960 m/s, which demonstrated that a giga Hertz SAW filter can be realized by utilizing the nanocrystalline diamond thin film.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.92-97
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• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.281-284
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• 2015

Digital image processing is utilized in various application fields by rapid development of memory cell. However, the noise occurs with various causes in the process of data processing process and various methods have been studied in order to remove such noises. In general, the image is damaged by the mixed noise which has different characteristics each other. This paper proposed a filter algorithm which processes the data according to shape of noise in order to mitigate the impact of the mixed noise added to the image. In addition, this paper compared this filter algorithm with the current methods and used PSNR(peak signal to noise ratio) as a criterion of judgment.