• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.301-304
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• 2002

This paper has been studied an A/D conversion system for precision weighing signal process In weighing system. A/D conversion has some problem.; offset drift voltage with environment situation and nonzero value of initial output voltage. The Offset voltage in analog circuit produces a drift of an output voltage before A/D conversion stage. This paper suggested the method of reducing the offset voltage by switching analog chopping circuit and making the initial output close to zero to enhance the swing range by D/A converter. Also, we have designed active filter and digital filter with Auto Zero Tracking algorithm for better signal process of the weighing system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.443-446
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• 2005

As modern society needs to process of acquisition, storage and transmission of much information, the importance of signal processing is increasing and various digital filters are used in the two-dimensional signal such as image. And kinds of these digital filters are IIR(infinite impulse response) filter and FIR(finite impulse response) filter. And FIR filter which has the phase linearity, the easiness of creation and stability is applied to many fields. In design of this FIR filter, flatness property is a important factor in pass-band and stop-band. In this paper, we designed a 2-D Circular FIR filter using the Bernstein polynomial, it is presented flatness property in pass-band and stop-band. And we simulated the designed filter with noisy test image and compared the results with existing methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.252-255
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• 2014

Image treatment is becoming mainstream as the demand for image restoration has drastically increased in the digital era. But in the process of acquiring, transmitting and treating video data, the salt and pepper noise damages the image. One of the major methods used for restoring images are SMF(standard median filter), CWMF(center weighted median filter) and SWMF(switching weighted median filter), but these filters all leave a bit to be desired in terms of removing noise and preserving edge. Therefore, a transformed median filter is suggested through the algorithm presented for the restoration of damaged images.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.118-120
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• 2021

In modern society, with the development of IoT technology, various digital equipment is being distributed in a wide range of fields such as CCTV and exploration robots. Accordingly, the importance of data processing is increasing, and various studies are being conducted to remove noise generated in the process of receiving data in the imaging field. Representative noise includes additive white Gaussian noise (AWGN), and existing filters for removing noise include an average filter (AF), an alpha trimmed average filter (A-TAF), and a median filter (MF). However, existing filters have a disadvantage in that they show somewhat insufficient performance in noise removal characteristics in high frequency areas. Therefore, in this paper, in order to effectively remove AWGN existing in the high frequency region, a weight filter according to a distance based on the standard deviation is proposed.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Journal of radiological science and technology
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• v.24 no.1
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• pp.67-73
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• 2001

In digital image processing, the homomorphic filtering approach is derived from an illumination-reflectance model of the image. It can also be used with an illumination-transillumnation model of X-ray film. Several X-ray images were applied to enhancement with histogram equalization and homomorphic filter based on an illumination-transillumination model. The homomorphic filter has proven theoretical claim of image density range compression and balanced contrast enhancement, and also was found a valuable tool to process analog X-ray images to digital images.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.69-74
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• 1985

In this paper five-order Butterworth Low pass active RC filter is designed by using FDNR (Frequency Dependent Ncgative Resistor) Method from LC ladder filter having the lowest sensitivity. In process of Transformation to SCF (Switched Capacitor Filter) from active RC filter, Bilinear Z Transfomation method is utilized. By the design of SCF using the bilinear Z transform method the problem of aliasing can be avoided, but the frequency distortion is generated. The transformation from analog filter to digital filter is not equal in the region of the cut off frequency caused by this effect. Avoiding the problem of this effect, we use prewarping method. The result shows that the prewarped SCF makes more remarkable improvement in the frequency distortion than SCF which is transformed by using bilinear Z transform.