• Journal of Biomedical Engineering Research
• /
• v.15 no.3
• /
• pp.281-288
• /
• 1994

In this paper, a new decomposition method of the interference EMG signal using MAMDF filtering and digital signal processor. The efficient software and hardware signal processing techniques are employed. The MAMDF filter is employed in order to estimate the presence and likely location of the respective templates which may include in the observed mixture, and high-resolution waveform alignment is employed in order to provide the optimal combination set and time delays of the selected templates. The TMS320C25 digital signal processor chip is employed in order to execute the intensive calculation part of the software. The method is verified through a simulation with real templates which are obtain ed from needle EMG. As a result, the proposed method provides an overall speed improvement of 32-40 times.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.12
• /
• pp.2300-2307
• /
• 2008

This study receives the noise transmitted in a constant audio frequency range through a microphone array in which the noise(like grease in a pan) occurs on the power supply line due to the troublesome partial discharge(arc). Then by going through a series of signal processing of removing noise, this study measures the distance and direction up to the noise caused by the troublesome partial discharge(arc) and monitors the result by displaying in the analog and digital method. After these, it determines the state of each size and judges the distance and direction of problematic part. When the signal sound transmitted by the signal source of bad insulator is received on each microphone, the signal comes only in the frequency range of 20 kHz by passing through the circuit of amplification and 6th low pass filter. Then, this signal is entered in a digital value of digital signal processing(TMS320F2812) through the 16-bit A/D conversion. By doing so, the sound distance, direction and coordinate of bad insulator can be detected by realizing the correlation method of detecting the arriving time difference occurring on each microphone and the algorithm of detecting maximum time difference.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.97-97
• /
• 2000

In this paper, a signal processing algorithm for software GPS receiver is proposed. The signal processor takes snapshot of the sampled If signal from the RF section of the GPS receiver. All the processing for code and carrier tracking and correlation are implemented using the digital signal processing techniques. In order to achieve fast code acquisition, correlation of the incoming GPS signal is performed using the FFT method, After code acquisition, to reduce the Doppler shift effect and increase the accuracy, the interpolation or the tracking are performed. The performance of the proposed processing algorithm is first evaluated using matlab/simulink. A signal acquisition board for sampling and logging GPS IF signal form the Mitel GPS RF chip set is constructed. In order to analyze the performance of the designed algorithm the experiments are performed and the results are analyzed.

• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.572-578
• /
• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.20 no.4
• /
• pp.1309-1319
• /
• 1996

The research for the classification of the natural defects in welding zone is performd using the neuro-pattern recognition technology. The signal pattern recognition package including the user's defined function is developed to perform the digital signal processing, feature extraction, feature selection and classifier selection, The neural network classifier and the statistical classifiers such as the linear discriminant function classifier and the empirical Bayesian calssifier are compared and discussed. The neuro-pattern recognition technique is applied to the classificaiton of such natural defects as root crack, incomplete penetration, lack of fusion, slag inclusion, porosity, etc. If appropriately learned, the neural network classifier is concluded to be better than the statistical classifiers in the classification of the natural welding defects.

• 제어로봇시스템학회:학술대회논문집
• /
• 1990.10a
• /
• pp.580-585
• /
• 1990

This paper presents a real time FECG signal monitoring system in which an adaptive multichannel noise canceller is implemented using a Texas Instruments TMS32020 digital signal processor. Abdominal ECG signal is applied as the desired output and 3 chest ECG signals as the reference input signals of the adaptive multichannel noise canceller whose coefficients are updated using the LMS algorithms.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.156-167
• /
• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of Institute of Control, Robotics and Systems
• /
• v.13 no.4
• /
• pp.385-391
• /
• 2007

A class D digital audio amplifier with small size, low cost, and high quality is positively necessary in the multimedia era. Since the digital audio amplifier is based on the PWM signal processing, it is improper to analyze the principle of signal generation using linear system theories. In this paper, a class D digital audio amplifier based ADSM (Advanced Delta-Sigma Modulation) is considered. We first model the digital audio amplifier and then explain the operation principle using variable structure control algorithm. Moreover, the ripple signal generated by the hysteresis in the comparator has a significant effect on the system performance. Thus, we present a method to find the magnitude and the frequency of the ripple signal using describing function. Finally, simulations and experiments are provided to show the validity of the proposed methods.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.1
• /
• pp.49-55
• /
• 2003

The use of digital filters in the signal process field is increasing rapidly with development of the modern industrial society. Especially, detail processors, Y/C separators, ghost removing filters, standard converters (NTSC to PAL or PAL to NTSC) and noise reducers, all of which use digital filters, tend to be used in digital video and audio processing, CATV and various communication fields. Generally, there are two different digital filters, the Rf (infinite impulse response) filter and the FIR (finite impulse response) filter in digital filter. In this paper, we have designed FIR filter which has the phase linearity and the easiness of creation. In the design of the FIR digital filter, the window function is used to alleviate the ripples caused by Gibbs Phenomenon around the cut off frequency of the band pass. But there're some problems to choose proper window function for the design destination due to its fixed values. Therefore, in this paper, we designed a modified Hanning window with new parameter which is adaptively chosen corresponding to design objectives. The digital filter was simulated to prove the validity of the model and it was compared with the Hamming, the Manning, the Blacknan and the Kaiser window function. And we have used peak side-lobe and transient characteristics as standard of judgement.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.5
• /
• pp.35-41
• /
• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.