• Title/Summary/Keyword: Digital Signal Processing

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Availability Verification of Feature Variables for Pattern Classification on Weld Flaws (용접결함의 패턴분류를 위한 특징변수 유효성 검증)

  • Kim, Chang-Hyun;Kim, Jae-Yeol;Yu, Hong-Yeon;Hong, Sung-Hoon
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.16 no.6
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    • pp.62-70
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    • 2007
  • In this study, the natural flaws in welding parts are classified using the signal pattern classification method. The storage digital oscilloscope including FFT function and enveloped waveform generator is used and the signal pattern recognition procedure is made up the digital signal processing, feature extraction, feature selection and classifier design. It is composed with and discussed using the distance classifier that is based on euclidean distance the empirical Bayesian classifier. Feature extraction is performed using the class-mean scatter criteria. The signal pattern classification method is applied to the signal pattern recognition of natural flaws.

A Study on Transmission Signal Design Using DAC to Reduce IQ Imbalance of Satellite-Mounted Synthetic Aperture Radar Transmitter (위성 탑재 영상레이다 송신기의 IQ 불균형 저감을 위한 DAC를 이용한 송신 신호 설계 기법에 관한 연구)

  • Lee, Young-Bok;Kang, Tae-Woong;Lee, Hyon-Ik
    • Journal of the Korea Institute of Military Science and Technology
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    • v.25 no.2
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    • pp.144-150
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    • 2022
  • The on-board processor of satellite synthetic aperture radar(SAR) generates transmission signal by digital signal processing, converts it into an analog signal. At this time, the transmission signal generated from the baseband requires the frequency modulation to convert it to the high-frequency band in order to improve the stability. General frequency modulation method using local oscillator(LO) causes IQ imbalance due to phase error/magnitude error and these error reduce performance of SAR. To generate transmission signal without phase/magnitude error, this paper suggests design method of the frequency modulation method using digital to analog converter(DAC) at on-board SAR. For design, this paper analyzes the characteristic of DAC mode and uses pre-compensation filter. To analyze the proposed method performance, performance index are compared with IQ imbalance signals. This method is suitable for on-board SAR using fast sampling DAC and has the advantage of being able to solve IQ imbalances.

Development of Test Software Program for Detection Array Module Signal Processing System (Array 검출모듈 신호처리 System의 Test Software Program 개발)

  • Park, Ge-O;Sung, So-Young;Kim, Young-kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.05a
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    • pp.379-382
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    • 2017
  • Shipping and logistics safety, security system is strengthening worldwide, the development of shipping and logistics safety security core technology for national security logistics system construction has been carried out. In addition, it is necessary to localize the Array Detection System, which is a core component of the container search machine, to cope with the 100% pre-inspection of the container scheduled for 2018 in the United States. In this paper, we propose a test software program developed by using TI-RTOS (Texas Instruments - Real Time Operating System) with a test digital signal processing board which is developed self development.

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Algorithm and Design of Double-base Log Encoder for Flash A/D Converters

  • Son, Nguyen-Minh;Kim, In-Soo;Choi, Jae-Ha;Kim, Jong-Soo
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.289-293
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    • 2009
  • This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

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A Study on the monitoring of tool wear in face milling operation (밀링공구의 마모 감시에 관한 연구)

    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.7 no.1
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    • pp.69-74
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    • 1998
  • In order to monitor the tool wear in milling operation, cutting force is measured as the tool wear increased. The digital signal processing methods are used to detect the tool wear . As AR parameter extract the feature of tool wear , it can be used as input parameter of pattern classifier. The FFT monitor the tool wear exactly , but it can not do real time signal processing. The band energy method can be used to real time monitoring of tool wear ,but int can degrade the exact monitoring.

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The Use of The Spectral Properties of Basis Splines in Problems of Signal Processing

  • Nasiritdinovich, Zaynidinov Hakim;Egamberdievich, MirzayevAvaz;Panjievich, Khalilov Sirojiddin
    • Journal of Multimedia Information System
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    • v.5 no.1
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    • pp.63-66
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    • 2018
  • In this work, the smoothing and the interpolation basis splines are analyzed. As well as the possibility of using the spectral properties of the basis splines for digital signal processing are shown. This takes into account the fact that basic splines represent finite, piecewise polynomial functions defined on compact media.

Design and Implementation of the 16-QAM Modem for 26㎓ FBWA system

  • Kim, Nam-il;Kim, Eung-bae
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.1346-1349
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    • 2002
  • This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

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A new automatic white balance algorithm using non-linear gain (Non-linear gain을 적용한 Automatic White Balance기법)

  • Yun, Se-Hwan;Kim, Jin-Heon
    • Proceedings of the KIEE Conference
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    • 2006.04a
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    • pp.27-29
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    • 2006
  • In this paper, we propose a new method of automatic white balance which is one of the image signal processing techniques. Our method is conceptually based on gray world assumption. However, while previous methods generate linear results as multiplying pixel values by a gain, our method generates non-linear results using the feature of B-Spline curves. The two merits of deriving non-linear results are preventing AWB failure from transforming strong color of high level into wrong color and well preserving original contrast of an input image.

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Design of Fast Parallel Floating-Point Multiplier using Partial Product Re-arrangement Technique (효율적인 부분곱의 재배치를 통한 고속 병렬 Floating-Point 고속연산기의 설계)

  • 김동순;김도경;이성철;김진태;최종찬
    • Proceedings of the IEEK Conference
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    • 2001.06e
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    • pp.47-50
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    • 2001
  • Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

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A Study on the Digital Implementation of Multi-layered Neural Networks for Pattern Recognition (패턴인식을 위한 다층 신경망의 디지털 구현에 관한 연구)

  • 박영석
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.12a
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    • pp.233-236
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    • 2000
  • 본 연구에서는 패턴 인식용 다층 퍼셉트론 신경망을 순수 디지털 논리회로 모델로 전환 구현할 수 있도록 새로운 논리뉴런의 구조, 디지털 정형 다층논리신경망 구조, 그리고 패턴인식의 응용을 위한 다단 다층논리 신경망 구조를 제안하고, 또한 제안된 구조는 매우 단순하면서도 효과적인 증가적인 가법적(Incremental Additive) 학습알고리즘이 존재함을 보였다.

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