• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.1
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• pp.43-50
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• 2016

This paper is on an acoustic echo canceller solving the double-talk problem by using the blind signal separation technology. The acoustic echo canceller may be deteriorated or diverged during the double-talk period. So we use the blind signal separation to detect the double talking by separating the near-end speech signal from the mixed microphone signal. The blind signal separation extracts the near-end signal from dual microphones by the iterative computations using the 2nd order statistical character in the closed reverberation environment. By this method, the acoustic echo canceller operates irrespective of the double-talking. We verified performances of the proposed acoustic echo canceller in the computer simulations. The results show that the acoustic echo canceller with this algorithm detects the double-talk periods well, and then operates stably without diverging of the coefficients after ending the double-talking. The merits are in the simplicity and stability.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1075-1080
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• 2010

There have been lots of researches for High Performance Digital Signal Processing performance enhancement on a GPU(Graphic Processor Unit). These kinds of parallelizing can enable massive signal processing, so we can have advantage's of processing various of signal processing standards with GPU. In this paper we introduce Low Density Parity Check(LDPC) which is one of the Foward Error Correction(FEC). And we have achieved computational time reduce by using CUDA as a parallelizing scheme.

• Journal of Sensor Science and Technology
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• v.16 no.3
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• pp.187-191
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• 2007

This paper presents a development of the multi-channel data acquisition/logging system for a sensor signal processing and a method of the evaluation and a temperature compensation for the A/D converters with the specific analog and digital circuit including the software. Also, we have designed a hardware and a software filters with smart algorithm for better signal processing of the proposed system. Software approach was adopted to obtain the stable data from A/D converter.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.503-506
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• 2001

There are four factors for patient monitoring : electrocardiography, blood pressure, temperature and respiration. While there are a lot of studies of E.C.C (electro-cardiography) monitoring system in the world, the studies of Respiratory system are not enough and leave much to be desired in the country. In this paper, we developed a respiratory system with the electrical impedance change of the lungs depending on the breath. Using the same electrode, we can monitor E.C.C and Respiration simultaneously, so we can monitor a patient's no-breathing state due to the central nerve paralysis in the emergency room easily. In this monitoring system, the analog part was made separated from the digital part for reducing power source noise and protecting patient from electric shock. The analog part consists of the several parts a high-frequency sine-wave generator, all amplifier for amplifying any impedance change signal, an analog processing part for rectifying and filtering. And the digital parts consists of three parts an AD convertor for converting analog signal to digital signal, digital filter, and a digital part for digital signal processing. This system's merits are using the same electrode with E.C.C and developing the multiple patient monitoring system easily.

• Journal of the Korean Data and Information Science Society
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• v.28 no.5
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• pp.1001-1019
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• 2017

The signal processing is a field of the electrical engineering but it is very much related with the time series analysis. Thesedays the commercial softwares are widely used by the reseachers. We have attempted to make a guide for using the R-package in the digital signal processing. It would be good to read the materials in each section first and to follow the plots in the section 8 and to run the attached R-codes. The article consists of (1) Fourier transform and Fourier inverse transform, (2) spectral analysis (3) parametric and non-parametric estimation for the period (4) filter design. Simple theoretical explanations are provided and R implementations are added.

• International Journal of Control, Automation, and Systems
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• v.1 no.4
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• pp.412-430
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• 2003

In many practical problems in signal processing and control, the signal values are often restricted to belong to a finite number of levels. These questions are generally referred to as "finite alphabet" problems. There are many applications of this class of problems including: on-off control, optimal audio quantization, design of finite impulse response filters having quantized coefficients, equalization of digital communication channels subject to intersymbol interference, and control over networked communication channels. This paper will explain how this diverse class of problems can be formulated as optimization problems having finite alphabet constraints. Methods for solving these problems will be described and it will be shown that a semi-closed form solution exists. Special cases of the result include well known practical algorithms such as optimal noise shaping quantizers in audio signal processing and decision feedback equalizers in digital communication. Associated stability questions will also be addressed and several real world applications will be presented.