• Title/Summary/Keyword: Digital Delay Line

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Design of the Transceiver for a Wide-Range FMCW Radar Altimeter Based on an Optical Delay Line (광 지연선 기반의 넓은 고도 범위를 갖는 고정밀 FMCW 전파고도계 송수신기 설계)

  • Choi, Jae-Hyun;Jang, Jong-Hun;Roh, Jin-Eep
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.11
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    • pp.1190-1196
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    • 2014
  • This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

A Design Method of Wide-band Filter with Optical Fiber and Directional Coupler (광파이버와 방향성결합기에 의한 광대역필터 구성법에 관한 연구)

  • 이채욱;김신환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.6
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    • pp.539-547
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    • 1992
  • Considering the field of high frequency or broad-band signal filtering with high speed, we pro-pose optical fiber filters which consist of directional couplers and optical fiber delay elements. Fiber delay line signal processor Is operated with Incoherent optical carrier because of Its simplicity. Due to the characteristics of the directional coupler which Is basic element of optical fiber filter a new design method which Is different from that of usual digital filter is required. By considering the characteristics of directional coupler and in order to make good use of the optical signal energy, we have given the design formulae and the conditions of optical fiber filters for the direct and the lattice form.

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Design of digitally controlled CMOS voltage mode DC-DC buck converter for high resolution duty ratio control (고해상도 듀티비 제어가 가능한 디지털 제어 방식의 CMOS 전압 모드 DC-DC 벅 변환기 설계)

  • Yoon, KwangSub;Lee, Jonghwan
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1074-1080
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    • 2020
  • This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

Design and Fabrication of Compressive Receiver for RFID Signal Detection (RFID 신호 탐지용 컴프레시브 수신기의 설계 및 제작)

  • Jo, Won-Sang;Park, Dong-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.3
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    • pp.321-330
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    • 2010
  • In this paper, the theoretical background and the specific implementation method of a compressive receiver for RFID signal detection as well as the design method of DDL(Dispersive Delay Line) and chirp LO are described. DDL, which is one of the main components of the compressive receiver, is designed to have $13{\mu}s$ dispersive delay time and 6 MHz bandwidth using the SAW technique based on $LiNbO_3$ material. The chirp LO is designed using DDS(Direct Digital Synthesizer). Also the compressive receiver is fabricated to be installed into the RFID reader. Test results show the maximum frequency error of 25 kHz for single signal input, the receiver sensitivity of -44 dBm, and the maximum frequency error is 75 kHz for 6 multi-tone input signals. These results indicate that the fabricated compressive receiver is working well even in dense RFID operating environments.

A Study on the Secure Authentication Method using SIP in the VoIP System (VoIP 시스템에서 SIP를 이용한 보안 인증기법에 관한 연구)

  • Lee, Young Gu;Kim, Jeong Jai;Park, Chan Kil
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.7 no.1
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    • pp.31-39
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    • 2011
  • VoIP service uses packet network of ip-based because that has eavesdropping, interception, illegal user as vulnerable elements. In addition, PSTN of existing telephone network is subordinate line but VoIP service using the ip packet provide mobility. so The user authentication and VoIP user's account service using VoIP has emerged as a problem. To solve the vulnerability of SIP, when you use VoIP services with SIP, this paper has made it possible to authenticate user's terminal by using proxy server and proxy server by using authentication server. In conclusion, sender and receiver are mutually authenticated. In the mutual authentication process, the new session key is distributed after exchanging for the key between sender and receiver. It is proposed to minimize of service delay while the additional authentication. The new session key is able to authenticate about abnormal messages on the phone. This paper has made it possible to solve the vulnerability of existing SIP authentication by using mutual authentication between user and proxy server and suggest efficient VoIP service which simplify authentication procedures through key distribution after authentication.

Performance Evaluation of Adaptive Equalizer in Mobile Communication Fading Channel (이동 통신 페이딩 채널에서 적응 등화기의 성능 평가)

  • 금홍식
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1992.06a
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    • pp.76-80
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    • 1992
  • We consider the tapped-delay line (TDL) equalizer with the few calculation quantity and the simplity, the decision feedback equalizer (DFE) with the good property for interference, and lattice equalizer(LE) with high insensitivity to roundoff noise in mobile communication fading channel. The used adaptive algorithm is the LMS algorithm and RLS algorithm. In this paper, we have evaluated the performance of the TDL equalizer, the decision feedback equalizer, and lattice-structured equalizer, for the digital signal corrupted by the impulsive noise and the white gaussian noise under the fading channel environment. From the results of error performance analysis, it is confirmed that lattice-structured equalizer has better performance than DFE equalizer and TDL equalizer.

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Coordinates Tracking Algorithm Design (표적 좌표지향 알고리즘 설계)

  • 박주광
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.3
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    • pp.62-76
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    • 2002
  • This paper describes the design of a Coordinates Tracking algorithm for EOTS and its error analysis. EOTS stabilizes the image sensors such as FLIR, CCD TV camera, LRF/LD, and so on, tracks targets automatically, and provides navigation capability for vehicles. The Coordinates Tracking algorithm calculates the azimuth and the elevation angle of EOTS using the inertial navigation system and the attitude sensors of the vehicle, so that LOS designates the target coordinates which is generated by a Radar or an operator. In the error analysis in this paper, the unexpected behaviors of EOTS that is due to the time delay and deadbeat of the digital signals of the vehicle equipments are anticipated and the countermeasures are suggested. This algorithm is verified and the error analysis is confirmed through simulations. The application of this algorithm to EOTS will improve the operational capability by reducing the time which is required to find the target and support especially the flight in a night time flight and the poor weather condition.

Digital Active Noise Control System Used Inverse Model (역모델을 이용한 디지털 능동 소음제어 시스템)

  • 정찬수;이강욱;정양응
    • The Journal of the Acoustical Society of Korea
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    • v.11 no.1E
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    • pp.56-63
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    • 1992
  • The poblem of active oise control has been analysed using a adaptive signal processing technique. In this methods, the adaptive signal processor or model predicts the primary sound wave travelling along the acoustic plant and generates the secondary source 180° out of phase which attempts to attempts to attenuate the undesired noise by destructive interference. In the solutions presented here, acoustic propagation delay is considered as a part of the model which used the FIR filter. The effects of error path and auxiliary path transfer functioin are anayzed and a new on=-line technique for error path modeling, adaptive delayed inverse modeling is presented. In this study, using these new concepts, our system can more reduce the noise level in duct to 5dB-15dB than only using LMS algorithm system.

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Digital firing control for high power thyristor converter (대용량 전력변환용 사이리스터 디지털 점호제어)

  • Lee Y.B.;Kim J.M.;Lim I.H.;Ryu H.S.;Song S.H.
    • Proceedings of the KIPE Conference
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    • 2003.07b
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    • pp.565-568
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    • 2003
  • The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac line, with a voltage corresponding to the desired converter delay angle. This circuit requires a large number of components (resistance and capacitor) and careful adjustment of the synchronization circuity In this paper a novel firing circuit is proposed for thyristor switch is elements. The proposed circuit is implemented on the basis of the analog cosine method using FPGA and microprocessor.

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A Zipper-based VDSL Modem with an Efficient Cyclic Extension (효율적 Cyclinc Extension을 갖는 Zipperqkdtlr의 VDSL 모뎀)

  • 위정욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10B
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    • pp.1793-1802
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    • 2000
  • In this paper we propose an efficient implementation technique for cyclic extension in VDSL(Very High bit-rate Digital Subscriber Line) systems using Zipper duplexing and analyze its performances under typical telephone channel environments. In Zipper-based VDSL systems each DTM(discrete-multitone) block is appended by both cyclic prefix(CP) and cyclic suffix(CS). The CP is inserte to prevent both intersymbol interference (ISI) and iterchannel interference (ICI) while the CS is appended to ensure orthogonality between the upstream and downstream carriers thus preventing near-end crosstalk (NEXT). However in order to implement the CP in the transmitter side of the VDSL system an additional hardware is required to append the latter part of each DMT symbol to the beginning of the DMT symbol. In this paper we propose a VDSL system with Zipper duplexing using only CS to reduce hardware complexity (memory and processing delay) required for implementation of CP. It is shown by computer simulation that the proposed approach has the same capacity under typical channel environments as the previous Zipper-based VDSL system using both CP and CS. even with a significantly lower hardware complexity.

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