• Nuclear Engineering and Technology
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• 제55권2호
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Progress in Superconductivity
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• 제9권2호
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• 한국통신학회논문지
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• 제21권1호
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 한국정보통신학회논문지
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• 제1권1호
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• pp.55-64
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• 1997

스펙트럼 확산통신(SS)은 CDMA 시스템의 핵심기술이다. 그러나, 스펙트럼확산 통신 방식에 있어서 가장 중요한 문제는 동기방식이다. 동기방식 에는 Delay Locked Loop (DLL), Tau-dither, SO(Synchronous Oscillator) 등이 있다. 그러나, 이러한 것들은 아날로그 동작이기 때문에 조정이 어렵고 크기가 크다는 단점이 있다. 본 연구에서는, Digital Delay Locked Loop (DDLL)을 설계 제작하고 그의 성능을 전력선 전송시스템 실험을 통하여 평가하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.36-40
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• 2003

On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. The control delay in digital controllers increases the dimension of the system transfer function one degree higher which makes the control system more complicate and more unstable. Based on the power stage analysis, a novel controller for the compensation voltages in DVRs is proposed by a feedforward control scheme. Proposed controller works well with the time delay in the digital control system. This paper also proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs in digital controllers. Proposed theory is verified by an experimental DVR system with a typical digital controller.

• 한국컴퓨터정보학회논문지
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• 제4권2호
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• pp.105-112
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• 1999

확산대역통신은 CDMA 시스템에서의 핵심기술이지만 SS통신에서의 문제점은 동기 방법이다. 동기방법에는 DLL(Delay Lock Loop), Tau-dither Loop, SO(Synchronous Osillator) 등이 있다. 그러나 아날로그 동작시에는 회로의 크기가 커지고 조정이 어려운 문제가 있어 본논문에서는 Digital Delay Lock Loop (DDLL)을 제안하고 실험을 통해 그 성능을 평가하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.155-159
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• 2001

In this paper, an on-line dead-time compensation method based on a time delay control approach is presented. The disturbance voltages caused by the dead time are estimated in an on-line manner by the time delay control without any additional circuits and off-line experimental measurements. And the estimated disturbance voltages are fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.

• 한국정보통신학회논문지
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• 제6권5호
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• pp.724-730
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• 2002

디지털 통신시스템에서는 인접채널에 대한 간섭을 최대한 줄이기 위하여 필연적으로 선형 전력증폭기가 요구된다. 선형 전력증폭기는 매우 다양하며, 그 중에서도 전방제환 전력증폭기는 구조상 광 대역이면서 선형화 정도가 매우 우수하기 때문에 많이 이용된다. 전방궤환 전력증폭기는 지연 선로의 손실로 인하여 전체효율이 감소한다. 본 논문에서는 이러한 지연 선로를 손실이 매우 작은 지연 여파기를 사용함으로써 효율과 선형성을 동시에 개선하였다. 측정 결과, ACLR이 약 17.43(dB) 개선되었으며, 이것은 지연 여파기를 사용함으로써 3.44(dB) 더 개선되었음을 나타낸다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.187-189
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• 1995

A Surface Acoustic Wave Gas sensor for NO, CO, H$_2$gas detection was designed fabricated, and tested. A delay line device was designed to composite a single mode SAW oscillator which enables to measure a SAW velocity. To reduce the effect of temperature and humidity, dual delay line oscillator circuit was used. And final output was measured by digital frequency counter. NO, CO, H$_2$gas were detected by WO$_3$thin film deposited on the path of the Delay Line.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.