• 한국조경학회지
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• 제47권3호
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• pp.31-38
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• 2019

본 연구는 남부지방에 흔히 식재하는 3개 조경수종을 대상으로 직접수확법을 통해 개방 생장하는 개체별 탄소저장 및 흡수를 계량화하고, 수종별 생장에 따른 탄소저감을 용이하게 산정하는 계량모델을 개발하였다. 연구 수종은 탄소저감 정보가 부재하는 동백나무, 배롱나무, 가시나무 등이었다. 유목에서 성목에 이르는 일정 간격의 줄기직경 규격을 고려하여 수종별로 10개체씩, 총 30개체의 수목을 구입하였다. 그리고 근굴취를 포함하는 직접 벌목을 통해 해당 개체의 부위별 및 전체 생체량을 실측하고, 탄소저장량을 산정하였다. 수종별 흉고직경 내지 근원직경의 줄기 원판을 채취하여 직경생장률을 분석하고, 연간 탄소흡수량을 산출하였다. 줄기직경을 독립변수로 생장에 따른 수종별 단목의 탄소저장과 연간 탄소흡수를 산정하는 활용 용이한 계량모델을 도출하였다. 이들 계량모델의 $r^2$은 0.94~0.98로서 적합도가 높았다. 흉고직경 10cm인 가시나무 단목의 탄소저장량과 연간 탄소흡수량은 각각 24.0kg/주 및 4.5kg/주/년이었다. 근원직경 10cm인 동백나무와 배롱나무의 경우는 각각 11.2kg/주 및 2.6kg/주/년, 8.1kg/주 및 1.2kg/주/년이었다. 이 탄소저장량은 가시나무 약 42L, 동백나무 20L, 배롱나무 14L의 휘발유 소비에 따른 탄소 배출량에 상당하였다. 또한, 상기한 직경의 가시나무, 동백나무 및 배롱나무 한 그루는 매년 각각 8L, 5L, 2L의 휘발유 소비에 따른 탄소 배출량을 상쇄하는 역할을 담당하였다. 본 연구는 식재 수목의 직접 벌목과 근굴취의 난이성을 극복하고, 남부지방 대상 조경수종의 생체량 및 탄소저감을 계량화하는 새로운 초석을 마련하였다.

• ETRI Journal
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• 제28권4호
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• pp.506-508
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• 2006

A frequency selective surface (FSS), whose unit cell consists of a ternary tree loop loaded with a modified tripole, is proposed to block multiple frequency bands. Target frequency bands correspond to Korean personal communication services, cellular mobile communication, and 2.4 GHz industrial, scientific, and medical bands. Through the adjustment of inter-element and inter-unit cell gaps, and adjustment of the length of elements, we present an FSS design method that makes the precise tuning of multiple resonance frequencies possible. Additionally, to verify the validity of our approach, simulation results obtained from a commercial software tool and experimental data are also presented.

• 한국디자인학회:학술대회논문집
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• 한국디자인학회 2003년도 봄 학술발표대회논문집
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• pp.186-187
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• 2003

• 한국CDE학회논문집
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• 제13권3호
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• pp.235-242
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• 2008

This paper proposes a method for improving the process plan quality by use of dimensional tolerances. Dimensioning and tolerancing plays a key role in manufacturing process plan because the final part must ensure conformance with the dimensions and tolerances in its drawing. As a first step for the improvement of process plan quality, two resultant tolerances in design and process plan should be compared each other, and so a tolerance chart is used for acquisition and comparison of the two tolerances. In addition to two kinds of design and manufacturing tolerances, operational sequences or paths for the resultant dimension and tolerance are additionally recognized for measuring the quality of process plan quantitatively. Rooted tree is applied to find the related paths for the manufacturing resultant tolerances. A quality coefficient is defined by the components of two tolerances and their relations, the paths related to manufacturing resultant tolerances and the difficulty of an operation. In order to improve the quality of manufacturing process plan, the paths that two kinds of tolerances are the same or different in the rooted tree are recognized respectively and a method for tolerance rearrangement is developed. A procedure for improving the quality is suggested by combining the coefficient and the tolerance rearrangement method. A case study is applied to illustrate the efficiency of improvement method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(3)
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• pp.63-66
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• 2001

In this paper, We propose the new interconnection network which is designed to edge numbering labeling using postorder traversal which can reduce diameter when it has same node number with Hypercube, which can reduce total node numbers considering node degree and diameter on Fibonacci trees and its jump sequence of circulant is Fibonacci numbers. It has a simple (shortest oath)routing algorithm, diameter, node degree. It has a spaning subtree which is Fibonacci tree and it is embedded to Fibonacci tree. It is compared with Hypercube. We improve diameter compared with Hypercube.

• Journal of applied mathematics & informatics
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• 제6권3호
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• pp.727-734
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• 1999

Let G be a connected graph of n vertices. The problem of finding a depth-first spanning tree of G is to find a connected subgraph of G with the n vertices and n-1 edges by depth-first-search. in this paper we propose an O(n) time algorithm to solve this problem on permutation graphs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(3)
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• pp.59-62
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• 2000

In this paper, We propose the new interconnection network which is designed to edge numbering method using inorder traversal a Fibonacci trees and its jump sequence is Fibonacci numbers. It has a simple (shortest path)routing algorithm, diameter, node degree. It has a spaning subtree which is Fibonacci tree and it is embedded Fibonacci tree. It is compared with Hypercube. We improve diameter compared with Hypercube on interconnection network measrtes.

• Communications for Statistical Applications and Methods
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• 제2권1호
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• pp.74-88
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• 1995

This article introduces a unified method of choosing the most explanatory and significant multiway partitions for classification tree design and analysis. The method is derived on the impurity reduction (IR) measure of divergence, which is proposed to extend the proportional-reduction-in-error (PRE) measure in the decision-theory context. For the method derivation, the IR measure is analyzed to characterize its statistical properties which are used to consistently handle the subjects of feature formation, feature selection, and feature deletion required in the associated classification tree construction. A numerical example is considered to illustrate the proposed approach.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.1049-1050
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• 2006

In this paper, we present the analysis of Tree-LDPC codes using EXIT(Extrinsic information transfer) charts methods. Two different EXIT charts schemes are compared. One is based on the closed form equation and the other is based on Monte-Carlo simulation. The thresholds by these two schemes match well with the threshold by DE(density evolution) scheme. Simulation performance is also shown with the obtained thresholds.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.371-374
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• 2000

This paper proposes a 16-bit ${\times}$ 16-bit multiplier for 2 twos-complement binary numbers with tree-like structure and implements it on a FPGA. The space and time complexity analysis shows that the 16-bit Tree-like multiplier represents lower circuit complexity and computes more quickly than both Booth array multiplier md Modified array multiplier.