• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1712-1717
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• 2007

This paper presents a derating design approach for reliability improvement of an aluminum electrolytic capacitor. The capacitor, usually mounted in a printed circuit board, is used to stabilize the circuit. The main failure mechanism of interest is dry-up of the electrolyte that is mainly caused by two stresses-temperature and voltage. The lifetime under these stresses is modeled as a function of these stresses and time using accelerated life testing. Quantitative variation in the lifetime, according to variations in these stresses, is investigated to perform the derating design of the capacitor so that the stress levels are selected to achieve required reliability measures for reliability improvement. Moreover, sensitivity analysis shows which stress would be a more important factor determining the lifetime.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1760-1765
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• 2007

This paper shows a derating design approach for LED reliability improvement. The LED is widely used in display devices or circuits. The main failure of interest is defined as 100% reduction of the light output intensity of LED resulting from corrosion due to stresses, i.e. temperature and humidity. The lifetime is varied according to the stress levels under where the LED operates so that correlation of the lifetime to these stress levels over time is modeled through accelerated life testings. A derating design approach to accomplish a required reliability level of LED is proposed to determine adequate the stress levels. In the approach, $B_{10}$ life, Failure rate, Sensitivity Analysis of LED are used as a reliability metric.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.5
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• pp.339-347
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• 2019

The power circuit design of an on-board S-band transmitter for KSLV-II with derating(operation of a component at less than its maximum rated specification to enhance reliability) is investigated. The power circuit of the transmitter consists of linear voltage regulators, DC/DC converters for regulating the DC supply, and diodes for reverse voltage protection. After analyzing the load current of the components, derating requirements are explored. Furthermore, power dissipation and junction temperature rise are considered with respect to the load current. The analysis is compared to the results from an engineering model of the transmitter. The temperature of the components is derated by >$40^{\circ}C$ in an environment where the ambient temperature is $+60^{\circ}C$, which is the acceptance test specification of high temperature.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.6
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• pp.743-749
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• 2010

This paper proposes a derating design method for improving system reliability by using a probabilistic approach. In the proposed design, the focus is upon system levels in determining derated levels of stresses such as temperature and current, unlike recent design approaches that focus on component levels. System reliability is evaluated using component reliability metrics that are given as functions of time and unknown stresses; this evaluation is based on a series system-reliability model. The variation in stress, which was not considered in previous derating designs, is introduced in the present design to account for the uncertainty in both environmental and operating conditions at the customer' hands. Optimization problems for system reliability improvement are formulated and solved using FORM to determine the best derating design. An example of a derating design for an electrical system shows the details of the proposed method and its applicability to systems design for reliability improvement.

• Journal of Applied Reliability
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• v.7 no.1
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• pp.1-11
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• 2007

This paper presents a derating design approach for reliability improvement of a regulator IC. The IC is usually used in SMPS. The main failure mechanism of interest is voltage drop due to the package delamination mainly caused by two stresses, i.e. temperature and current. The lifetime under stresses is modeled as a function of stresses and time using accelerating life testings. Quantitative and qualitative variation in lifetime according to stress variations are investigated using the modeled lifetime. Stress levels would be determined to achieve required reliability levels in the aspect of derating design for reliability.

• Journal of Applied Reliability
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• v.9 no.2
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• pp.149-163
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• 2009

This paper intends to suggest a design to reduce the thermal load of a hand-carried ultrasound (HCU) system, with the aim of increasing the product life. To design ways to reduce the heat load, the surface temperatures of key parts of an HCU system were measured as the 4 system cooling fans, which have a direct relation to the system life, were operated normally. When the derating rate of 80% was applied while the fans of the HCU system were operated abnormally, it was observed that the key image processing parts exceeded the surface temperature (TC) with consideration to derating. Since the part surface temperature did not exceed the derated level when the regulated voltage was derated from 12V to 9V, it is expected to lower the operating voltage of the fans to 9V to increase the fan and HCU system lifetime by 1.8 times.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.789-794
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• 2014

The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.1
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• pp.72-78
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• 2015

Recently, the usage of the satellite is increased more and more in the areas that are communication, weather, marine, optical, radar etc. The functions of the Satellite are evolving from passive transponder to active transponder by the developing of a technology. Advanced countries in satellites install the DCAMP for increase of bandwidth efficiency, improvement of QoS by interference rejection. DCAMP includes many digital components in order to implement functions. Thus, these kinds of active transponders consume much more power compared to passive transponder and then increase the heat. In this paper, we discuss the TVAC test result of DCAMP in EQM(Engineering Qualification Model) level. The paper shows the test results of digital gain control in order to verify DCAMP status under the TVAC test. In addition, the temperature and heat condition of main components from viewpoint of derating will be treated through the official environment test for qualification.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.3
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• pp.268-274
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• 2007

In general, rocket or satellite circuit designers focus on reducing temperature of electronic devices in order to enhance electronic unit's reliability. This paper describes the quantitative analysis result of activation energy as well as device temperature effects to the system reliabilities. The quantitative analysis result shows that activation energy of device has more effects on system reliability than temperature does. And this paper suggests a strategy for enhancement of reliability during devices placement on PCB with simulation results.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.7-11
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• 2017

This paper describes a design concept of NPC1 power stack for 1500VDC megawatt level solar inverter. This stack uses three latest half-bridge IGBT modules with highest power density and operation junction temperature, which enable realization of power level beyond 1MW without paralleling. Critical design concept on loop inductance is explained. Dynamic characteristics are verified by double-pulse test. Thermal characteristics and output power limits are verified by thermal test. Temperature-sensitive component on PCB as output power constraint is identified. Different PCB repositioning solutions are tested to give the overall output power thermal derating curves, which enable output power of 1.15MW at $T_A=55^{\circ}C$ with $15^{\circ}C$ thermal margin. The power stack characteristic and performance change under different thermal environment is further analyzed.