• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.61-69
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• 2008

In order to evaluate the performance of priority queues for future event list in discrete-event simulations, models representing patterns of enqueue and dequeue processes are required. The time complexities of diverse priority queue implementations can be compared using the performance models. This study aims at developing such performance models especially under the environment that a developed simulation model is used repeatedly for a long period. The developed performance model is based on multi-stage Markov process models; probabilistic patterns of enqueue and dequeue are considered by incorporating non-homogeneous transition probability. All necessary parameters in this performance model would be estimated by analyzing a results obtained by executing the simulation model. A case study with a war game simulation model shows how the parameters defined in muti-stage Markov process models are estimated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.