• IT SoC Magazine
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• s.11
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• pp.45-45
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• 2006

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.90-93
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• 2002

In this work, an efficient lifting implementation of invertible deinterlacing is proposed. The invertible deinterlacing is a technique developed for intra-frame-based video coding as a preprocessing. Unlike the conventional deinterlacing, it preserves the sampling density and has the invertibility. For a special selection of filters, it is shown that the deinterlacing can be implemented efficiently by an in-place computation. It is also shown that the deinterlacing can be combined with the lifting discrete wavelet transform (BWT) employed in JPEG2000. A bit modification of the original lifting DWT is shown to provide the simultaneous implementation of deinterlacing. This fact makes the proposed technique attractive for the application to Motion-JPEG2000. The inverse transform and the reversible lifting implementation are also discussed.

• Journal of the Korean Data and Information Science Society
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• v.19 no.3
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• pp.723-734
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• 2008

The main reason for deinterlacing is frame-rate conversion. The other reason for deinterlacing is of course improve clarity and reduce flicker. Using a deinterlacer can help clarity and stability of the image. Many deinterlacing algorithms are available in image processing literatures such as ELA and E-ELA. This paper propose a new statistical deinterlacing algorithm based on statistical tests such as the Bartlett test, the Levene test and the Kruskal-Wallis test. The results obtained from the proposed algorithms are found to be comparable to those from many well-known deinterlacers. However, the results in the proposed deinterlacers are found to be more efficient than other deinterlacers.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.355-362
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• 2009

A new intra field deinterlacing algorithm with edge map in the image block is introduced. Conventional deinterlacing methods usually employ edge-based line average algorithm within pixel-by-pixel approach. However, it is sensitive to variation of intensity. To reduce this shortcoming, we proposed edge direction vector computed by edge map, and also its interpolation technique. We first introduce an edge direction vector, which is computed by Sobel mask, so that finer resolution of the edge direction can be acquired. The proposed edge direction vector oriented deinterlacer operates by identifying small pixel variations in five orientations, while weighted averaging to estimate missing pixel. According to the edge direction of the direction vector, we calculate weights on each edge direction. These weight values multiplied by the candidate deinterlaced pixels in order to successively build approximations of the deinterlaced sequence.