• Journal of Communications and Networks
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• v.5 no.1
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• pp.82-89
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• 2003

In this paper, an efficient threshold-based filtering (TF) buffer management scheme is proposed. The TF is capable of minimizing the overall loss performance and improving the fairness of buffer usage in a shared buffer packet switch. The TF consists of two mechanisms. One mechanism is to classify the output ports as sctive or inactive by comparing their queue lengths with a dedicated buffer allocation factor. The other mechanism is to filter the arrival packets of inactive output ports when the total queue length exceeds a threshold value. A theoretical queuing model of TF is formulated and resolved for the overall packet loss probability. Computer simulations are used to compare the overall loss performance of TF, dynamic threshold (DT), static threshold (ST) and pushout (PO). We find that TF scheme is more robust against dynamic traffic variations than DT and ST. Also, although the over-all loss performance between TF and PO are close to each other, the implementation of TF is much simpler than the PO.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.44 no.3
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• pp.22-32
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• 2021

To meet rapidly changing market demands, manufacturers strive to increase both of productivity and diversity at the same time. As a part of those effort, they are applying flexible manufacturing systems that produce multiple types and/or options of products at a single production line. This paper studies such flexible manufacturing system with multiple types of products, multiple Bernoulli reliability machines and dedicated buffers between them for each of product types. As one of the prevalent control policies, priority based policy is applied at each machines to select the product to be processed. To analyze such system and its performance measures exactly, Markov chain models are applied. Because it is too complex to define all relative transient and its probabilities for each state, an algorithm to update transient state probability are introduced. Based on the steady state probability, some performance measures such as production rate, WIP-based measures, blocking probability and starvation probability are derived. Some system properties are also addressed. There is a property of non-conservation of flow, which means the product ratio at the input flow is not conserved at the succeeding flows. In addition, it is also found that increased buffer capacity does not guarantee improved production rate in this system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3542-3566
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• 2018

In this paper, we investigate a buffer-aided wireless powered cooperative communication network (WPCCN), in which the source and relay harvest the energy from a dedicated power beacon via wireless energy transfer, then the source transmits the data to the destination through the relay. Both the source and relay are equipped with an energy buffer to store the harvested energy in the energy transfer stage. In addition, the relay is equipped with a data buffer and can temporarily store the received information. Considering the buffer-aided WPCCN, we propose two buffer-aided relaying protocols, which named as the buffer-aided harvest-then-transmit (HtT) protocol and the buffer-aided joint mode selection and power allocation (JMSPA) protocol, respectively. For the buffer-aided HtT protocol, the time-averaged achievable rate is obtained in closed form. For the buffer-aided JMSPA protocol, the optimal adaptive mode selection scheme and power allocation scheme, which jointly maximize the time-averaged throughput of system, are obtained by employing the Lyapunov optimization theory. Furthermore, we drive the theoretical bounds on the time-averaged achievable rate and time-averaged delay, then present the throughput-delay tradeoff achieved by the joint JMSPA protocol. Simulation results validate the throughput performance gain of the proposed buffer-aided relaying protocols and verify the theoretical analysis.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.94-97
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• 1999

In this paper, a new real-time neural network connection admission controller is proposed. The proposed controller measures traffic flows, cell loss rate and cell delay periodically each classes. The Neural network learns the relation between those measured information and service quality by real-time. Also the proposed controller uses the DWRR multiplexer with buffer dedicated to every traffic source in order to measure the delay that cells experience in buffer. Experimental result shows that the proposed method can control effectively heterogeneous traffic sources with diverse QoS requirement.

• The Journal of the Acoustical Society of Korea
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• v.8 no.5
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• pp.95-101
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• 1989

For developing new algorithms or dedicated hardware by using general purpose Digital Signal Processor chip, emulator H/W and simulator S/W are indispensible. But the most of DSP emulators have limitations on H/W flexibility according to their generalized architectures. In this paper, a DSP evaluation system for real time signal processing was developed using TMS 32020. The I/O buffers storing acquisition data of the system were designed to have variable length $(1\sim2048samp1es) &$ sampling frequency $l00\sim8KHz$.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.11-19
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• 1994

Turnaround time of a job performing frequent disk I/O operations is greatly affected by I/O bottleneck which incurs due to the large gap in the speeds of I/O devices and the CPU. This paper proposes to employ a Write Dedicated Buffer(WDB) in disk arrays to improve the response time for read requests and analyzes the scheduling policies and the efficiency of the WDB. Through a series of simulations we show that, among the three policies examined, the partial stripe join(PSJ) policy is the most effective in terms of response time for both read and write requests and that, especially when using a WDB on declustered arrays, improvement of response time for read requests becomes greater as the request rate increases.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.1-5
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• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.

• Korean Management Science Review
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• v.28 no.3
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• pp.15-29
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• 2011

In this paper, we consider a system working at both primary service and secondary service. A server can switch between the primary service and the secondary service or it can be assigned to secondary service as a dedicated server. A service policy is characterized by the number of servers dedicated to the secondary service and a rule for switching the remaining servers between two services. The primary service system is modelled as a Markovian queueing system and the throughput is a function of the number of servers, buffer capacity, and service policy. And the secondary service system has a service level requirement strategically determined to perform the service assigned. There is a revenue obtained from throughput and costs due to servers and buffers. We study the problem of simultaneously determining the optimal total number of servers, buffers, and service policy to maximize profit of the system subject to both an expected customer waiting time constraint of the primary service and a service level constraint of the secondary service and develop an algorithm which can be successfully applied with the small number of computations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.119-130
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• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.223-226
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• 1998

In the Input Buffer Switch using the intial stage FIFO memory structure, It has pointed the Throughput limitation to the percent of 58.6 due to HOL(Head of Line) blocking in the DBP(Dedicated Buffer with Pointer) method, During that time, To overcome these problems, The prior papers have proposed the complicated Arbitration algorithms and Non-FIFO memory structures. and These showed the improved Throughput. But, Now, To design high speed ATM Switch which need to the tens of Giga bit/s or the tens of Tera bit/s. It has more difficulty in proceeding the priority of majority and the complicated Cell Scheduling, because of the problem in operating the control speed of the ratio of N to scanning each port and scheduling the Cell. In this paper, To overcome these problems, We could show more the improved performance than the existing DBP Window policy to design high speed ATM Switch.