• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• Information Systems Review
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• v.25 no.1
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• pp.129-143
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• 2023

In the era of big data, the field of artificial intelligence is showing remarkable growth, and in particular, the image classification learning methods by deep learning are becoming an important area. Various studies have been actively conducted to further improve the performance of CNNs, which have been widely used in image classification, among which a representative method is the Convolutional Recurrent Neural Network (CRNN) algorithm. The CRNN algorithm consists of a combination of CNN for image classification and RNNs for recognizing time series elements. However, since the inputs used in the RNN area of CRNN are the flatten values extracted by applying the convolution and pooling technique to the image, pixel values in the same phase in the image appear in different order. And this makes it difficult to properly learn the sequence of arrangements in the image intended by the RNN. Therefore, this study aims to improve image classification performance by proposing a novel hybrid method of CNN and RNN applying the concepts of encoder and decoder. In this study, the effectiveness of the new hybrid method was verified through various experiments. This study has academic implications in that it broadens the applicability of encoder and decoder concepts, and the proposed method has advantages in terms of model learning time and infrastructure construction costs as it does not significantly increase complexity compared to conventional hybrid methods. In addition, this study has practical implications in that it presents the possibility of improving the quality of services provided in various fields that require accurate image classification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.523-529
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• 2017

In this paper, we propose an efficient sphere decoding scheme that reduces computational complexity by combining receive and transmit ordering techniques in generalized spatial modulation systems, where the indexes of activated transmit antennas as well as the transmit symbols are exploited to transfer information to the receiver. In this scheme, the receive signals are optimally ordered so that the calculation for a candidate solution outside the sphere is terminated early to lower the computational complexity. In addition, the transmit ordering technique is applied to first search for candidate symbols and activated antennas having higher probabilities to further reduce the computational complexity. Simulation results show that the proposed doubly ordered sphere decoding scheme provides the same bit error rate performance with the conventional sphere decoding method and the sphere decoder employing only the receive ordering technique while it requires lower computational complexity.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.513-526
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• 2010

In this paper, we propose a de-blocking filter for improvement of coding efficiency and computational complexity reduction on a high definition video coding. Recently, the H.264/AVC standard-based research for high definition video coding method is under way because the amount of used of high definition videos is on the increase. The H.264/AVC de-blocking filter is designed for low bitrate video coding and it improves not only the subjective quality but also coding efficiency by minimizing the blocking artifact. However, the H.264/AVC de-blocking filter that strong filtering is performed is not suitable in a high definition video coding which occurs relatively low blocking artifact. Also, the conventional de-blocking filter has high computational complexity in decoder side. The computational complexity of the proposed method is reduced about maximum 8.8% than conventional method. Furthermore, the coding efficiency of the proposed method is about maximum 7.3% better than H.264/AVC de-blocking filter.

• Journal of Broadcast Engineering
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• v.4 no.1
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• pp.32-43
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• 1999

This paper addresses schemes which securely transmit voice and data information under the worst communication environment using the frequency hopping(FH) communication system to avoid monitoring or interference against enemy. In case of using the conventional FEC and bit interleaving scheme. the processing time for error control coding and bit interleaving due to system complexity is highly demanded. In this paper. the effective information coding scheme of maprity error correction and block interleaving compatible to the proposed FH communication system is proposed to transmit voice or data (I6Kbps. 4.8Kbps. 2.4Kbps. 1.2Kbps, O.6Kbps) under the worst FH communication channel. In transmitter. low rate data signals are configured to majority data blocks. and transmitted repeatedly to FH channel which are structured to 20Kbps hopping frame cells. In receiver. the received data are decoded block by block, and taken majority error correction. Consequently. burst or random errors are corrected at the block deinterleaver and the majority decoder. The proposed coder structure reduces the coding/decnding processing time as well as the jamming interferences, and further simplify the data processing complexity for FH communication. Improved performance of the proposed scheme was verified under simulated channel environments.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2473-2483
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• 2000

In this paper, The turbo code is used to effectively remove noise which is generated on the image communication channel. Turbo code had excellent decoding performance. However, it had limitations for real time communication because of the system complexity and time delay in decoding procedure. To overcome this problem, this paper proposed a new SRI(Semi Random Interleaved algorithm, which decrease the time delay, when the image data, which reduced the interleaver size of turbo code encoder and decoder, transmitted. The SRI algorithm was composed of 0.5 interleaver size from input frame sequence. When the data inputs in interleaver, the data recorded by row such as block interleaver. But, When the data read in interleaver, the data was read by randomly and the next data located by the just address simultaneously. Therefore, the SRI reduced half-complexity when it was compared with pre-existing method such as block, helical, random interleaver. The image data could be the real time processing when the SRI applied to turbo code.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.123-132
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• 2011

Recently, DVC (Distributed Video Coding) is receiving a lot of attention as one of the low complexity video encoding techniques suitable for various applications with computation-limited and/or power-limited environment, and is being actively studied for improving the coding efficiency. This paper proposes a rate-distortion based selective block encoding scheme. First, the motion information is obtained in the process of generating side information at decoder and received through the feedback channel, and then, based on this information, the proposed method performs a selective block encoding based on rate-distortion optimization. Experimental results show that the performance of the proposed scheme reaches up to 2.2 dB PSNR gain over the existing scheme. Moreover, it is shown that the complexity can be reduced by encoding parts of region considering rate-distortion cost.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.41-52
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• 2011

It is important to reduce computational complexity of de-blocking filter for real-time implementation, because it accounts for a great part of total computational complexity of the decoder. Because there are a lot of conditional branches and memory accesses in a decoding loop, it is not easy to speed up the de-blocking filter. Therefore, this paper presents a new algorithm of de-blocking filter minimizing conditional branches and memory accesses. The proposed structure of de-blocking filter enables filter operation to parallelize by software pipelining. The proposed optimization method was implemented on a TMS320DM6467 EVM board and we achieved approximately 46% cycle reduction, compared with that of FFmpeg.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.117-122
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• 2007

For multiple antenna systems, we consider the hybrid iterative detection of the maximum a posteriori probability(MAP) detection and the linear detection such as the minimum-mean-square-error(MMSE) filtering with soft cancelation. We devise methods to obtain both the lower complexity of the linear detection and the superior performance of the MAP detection. Using the a prior probability of the coded bit which is extrinsic of the outer decoder, we compute the threshold of grouping and determine the detection scheme symbol by symbol. Through the simulation results, it is shown that the proposed receiver obtains the superior performance to the MMSE detector and the lower complexity than the MAP detector.