• Journal of Institute of Control, Robotics and Systems
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• v.5 no.2
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• pp.220-227
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• 1999

The position control accuracy of a robot arm is significantly deteriorated when a long slender arm robot is operated at a high speed. In this case, the robot arm needs to be modeled as a flexible structure, not a rigid one, and its control system needs to be designed with its elastic modes taken into account. In this paper, the vibration control scheme of a one-link flexible manipulator using adaptive input shaper in conjunction with PID controller is presented. The robot consists of a flexible arm manufactured with a thin aluminium plate, an AC servo motor with a harmonic drive for speed reduction, an optical encoder and an accelerometer. On-line identification of the vibration mode is done using the pruned decimation-in-time FFT algorithm to estimate the parameter of the input shaper. Experimental results of the flexible manipulator with a PID controller and input shaper are provided to show the effectiveness of the advocated controllers.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.497-500
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• 2003

In this paper, a new filter structure to improve frequency response characteristics in CIC(Cascaded Integrator-Comb) decimation filters is proposed. Conventional filters improve passband characteristics, but they make worse slinging band characteristics. In this paper, we propose a new filter which is called IFOP(Interpolated Fourth-Order Polynomials). By using this proposed filter, passband droop and aliasing band attenuation are simultaneously improved. Since proposed filter needs only one multiplication computation is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, implementation cost of the proposed filter is compared with those of conventional filters.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.2
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• pp.80-87
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• 1994

Fetal monitoring is a routine procedure to obtain a record of physiologic functions during pregnancy and labor. It is required to determine fetal heart frequency accurately. There are various types of fetal heart rate(FHR) determination and the most frequently applied method is transabdominal Doppler ultrasound. However, in the case of weak or noise corrupted Doppler ultrasound signals, conventional peak detections and the autocorrelation function method have many difficulties to determine FHR precisely. Also the autocorrelation function is effected by threshold level and window size. To solve these problems, the high resolution pitch determination algorinthm is introduced to detect FHR from Doppler ultrasound signals. This scheme digitally processes Doppler ultrasound signal for digital rectification, envelope detection, decimation and correlation calculation of two interconnected segments and then FHR is determined by its maximal value. Even in the case of a greatly smeared noise signal, this algorithm is able to search FHR more accurately than autocorrelation function by means of compensating FHR with a constant correlation threshold. This algorithm is simulated by 386-MATLAB on PC 486/DX and verified that it is superior to the autocorrelation function method.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2475-2478
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• 2003

CELP계열의 부호화기인 G.723.1 5.3kbps ACELP를 기반으로 하여 음질을 유지하면서 전송률을 낮출 수 있는 새로운 부호화 방법을 제안한다. 본 논문에서 적용한 부호화 방법은 음성 합성시 파라미터로 사용되는 지속시간 변경에 의해 CELP형 보코더의 전송률을 감소하고자 한다. 먼저 음성을 보코더 입력단에 입력하기 전 지속시간을 FFT 변환 특성을 이용해 음색의 변경 없이 지속시간을 줄임으써 계산시간을 줄이고 진폭과 위상 각각 1/2ⁿ배의 interpolation과 Decimation을 수행하여 부호화한다. 이렇게 부호화된 데이터는 G.723.1 복호화를 거치고, 다시 FFT point의 1/2ⁿ배 point로 IFFT과정을 수행함으로써 스팩트럼의 변경 없이 지속시간을 변경하여 원 음성을 합성하게 된다. G.723.1 보코더를 통과한 후 파형을 복원 실험한 결과 기존의 5.3kbps ACELP보다 46％정도 감소하였다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.348-352
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• 2017

In this paper, we propose a high resolution A/D converter for a sensor interface that processes low frequency AC signals. A 6b SAR ADC with low power consumption and a 11b incremental ADC with high resolution are combined together to perform 15b resolution. Conventional hybrid ADC has a disadvantage that it can convert t only DC signal, but in this paper, it is possible to convert data to AC signal by increasing input range of incremental ADC. The decimation filter is implemented on-chip. The designed Hybrid ADC operates at supply voltage of 1.8V and consumes the current of 6.98uA. The OSR (oversampling ratio) is 90. And SFDR, SNDR, ENOB and FoMs are 96.59dB, 88.47dB, 14.4-bit and 139.5dB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1092-1099
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• 2001

본 논문에서는 무선 통신 시스템의 중간주파수 처리 단을 디지털로 신호 처리하는 DDC(Digital Down Converter)의 저전력 아키텍처를 제안한다. FIR 필터의 계산량을 줄이기 위해서 개발된 Interpolated FIR 필터가 DDC의 데시메이션 필터로 널리 사용되고 있다. 본 논문은 이와 같은 Interpolated FIR 필터의 개념이 IIR 필터에도 적용될 수 있음을 보이고, 전력 소모와 구현 면적이 기존의 Interpolated FIR 구조보다 더욱 감소된 Interpolated IIR 필터 구조를 제안하였다. CDMA IS-95 DDC 사양의 데시메이션 필터를 FIR 구조, Interpolated FIR 구조, IIR 구조, Interpolated IIR 구조로 구현하여 이 4가지 구조들의 전력소모와 구현 면적을 비교하였으며 제안된 Interpolated IIR 구조가 기존의 Interpolated FIR 구조에 비하여 15.2%의 소모전력 감소와 35.3%의 구현면적의 감소를 달성할 수 있음을 보인다.

• Journal of Biomedical Engineering Research
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• v.12 no.4
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• pp.295-302
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• 1991

In this paper, the inter- and intra-frame distortions in the gray levels of a series of fluorescein ocular fundus photographs are corrected. For doing this, the background images are extracted from original images using the image blurring effect by decimation, and then shading corrected images are obtained by subtracting the background images from the original images pixel by pixel. In a series of fluorescein ocular fundus photographs, after the gray scale distoriton is corrected, the intensity volumes of dye leakage are measured and represented by a graph. These data may be useful for the prediction of prognosis and the therapeutic management.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.632-638
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• 2001

본 논문에서는 AMR(Adaptive Multi-Rate)를 이용하여 광대역 음성부호화기를 설계하였다. 16kHz로 샘플링된 입력 신호를 QMF 필터에 의해 두 개의 대역으로 나누어, 각각 decimation하여 두 개의 8kHz 샘플링 신호로 변환시킨 후 저대역(0Hz-3400Hz)의 신호와 고대역(3400Hz∼7000Hz)의 신호로 나누어 각각 부호화한다. 나누어진 두 개의 협대역 음성신호는 AMR(Adaptive Multi-Rate)과 ATC(Adaptive Transform Coding)을 사용하여 각각 부호화되어 전송된다. 두 대역으로부터 부호화된 정보는 20.2kbps에서 12.75kbps까지의 전송률을 갖고, 수신단에서는 각 대역을 AMR과 ATC 방법으로 역부호화하여 음성신호를 합성한다. 설계된 광대역 음성부호화기의 성능을 평가하기 위해 ITU-T의 표준안인 G.722를 포함하여 MOS 시험을 하였다.