• Journal for History of Mathematics
• /
• v.18 no.3
• /
• pp.55-66
• /
• 2005

In our school mathmatics, the irrational numbers and the real numbers are defined and instructed on the basis of decimal fractions. In relation to this fact, we identified the essences of the real number and the irrational number defined by the decimal fractions through the historical analysis. It is revealed that the formation of real numbers means the numerical measurements of all magnitudes and the formation of irrational numbers means the numerical measurements of incommensurable magnitudes. Finally, we suggest instructional plan for the meaninful understanding of the real number concept.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.12 no.5
• /
• pp.6-11
• /
• 1975

반복형 그래이 부호 중 14진 및 16진 부호용 디지트 절차(digit sequence 또는 DS)의 여러가지 특성에 관하여 논하였으며 그것들을 통일적으로 기적할 수 있는 PDS는 각각 31종 및 11종이 있다는 것을 명백히 하였다. 그리고 이 PDS들에 회전변환과 순렬변환을 실시하여 얻을 수 있는 DS의 총수와 각종 특수 DS의 성질에 관하여도 논하였으며 대칭형 DS를 이용한 14진 및 16진 GC Counter를 설계하여 그것들의 동작을 실험에 의하여 확인하였다. Investigations on some characteristics of Tetra-Decimal and Hexa-Decimal recycling Gray co de (GC)-digit sequence(DS) are carried out, and, 31 and 11 kinds of prime digit sequence(PDS) are proposed respectively. From these PDS, by means of rotational conversion and permutational conversion, the numbers of all DS are obtained, and also the characteristics of some special DS are studied. Tetra Decimal and Hexa-decimal GC counters are designed using symmetrical DS, and, their operations are experimentally verified.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.55 no.11
• /
• pp.491-494
• /
• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Journal of Educational Research in Mathematics
• /
• v.17 no.3
• /
• pp.233-251
• /
• 2007

The purpose of this study was to propose instructional methods using base-ten blocks in teaching the division of decimal for 5th grade students by analyzing the process of their conceptual comprehension. The students in this study were found to understand the two main meanings of the division of decimal, distribution and area, by modeling them with base-ten blocks. They were able to identify the algorithm through the use of base-ten blocks and to understand the principle of calculations by connecting the manipulative activities to each stage of algorithm. The students were also able to determine using base-ten blocks whether the results of division of decimal might be reasonable. This study suggests that the appropriate use of base-ten blocks promotes the conceptual understanding of the division of decimal.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.3
• /
• pp.50-58
• /
• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of Educational Research in Mathematics
• /
• v.14 no.1
• /
• pp.1-17
• /
• 2004

According to the 7-th curriculum, irrational number should be introduced using repeating decimals in 8-th grade mathematics. To do so, the relation between rational numbers and repeating decimals such that a number is rational number if and only if it can be represented by a repeating decimal, should be examined closely Since this relation lacks clarity in some text books, irrational numbers have only slight relation with repeating decimals in those books. Furthermore, some text books introduce irrational numbers showing that $\sqrt{2}$ is not rational number, which is out of 7-th curriculum. On the other hand, if we use numeral 0 as a repetend, many results related to repeating decimals can be represented concisely. In particular, the treatments of order relation with repeating decimals in 8-th grade text books must be reconsidered.

• Journal of Elementary Mathematics Education in Korea
• /
• v.11 no.1
• /
• pp.1-21
• /
• 2007

The purpose of this study was to propose instructional methods using base-ten blocks in teaching the multiplication of decimal for 5th grade students by analyzing the process of their conceptual comprehension of multiplication of decimal. The students in this study were found to understand various meanings of operations (e.g., repeated addition, bundling, and area) by modeling them with base-ten blocks. They were able to identify the algorithm through the use of base-ten blocks and to understand the principle of calculations by connecting the manipulative activities to each stage of algorithm. The students were also able to determine whether the results of multiplication of decimal might be reasonable using base-ten blocks. This study suggests that appropriate use of base-ten blocks promotes the conceptual understanding of the multiplication of decimal.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.4
• /
• pp.115-124
• /
• 2015

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.11
• /
• pp.56-65
• /
• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of Korean Library and Information Science Society
• /
• v.39 no.3
• /
• pp.299-320
• /
• 2008

This study examined the historical background and structural characteristics of the UDC(Universal Decimal Classification) standard edition which has been created from the entire content of the Master Reference File database. We made a comparison of the structural characteristics between UDC standard edition and Korean abridged edition. UDC is a hybrid of two kinds of documentary classification scheme, that is enumerative and analytico-synthetic, and its structure reflects this feature. It is found that UDC standard edition extended the universality and synthetic method using its auxiliary tables compare to Korean abridged edition.