• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1217-1226
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• 1989

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters-heart rate, morpholigy, axis, and ST segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory unit is designed to decrease the delay time caused by data transfer between processors and be which the delay time can be taken 1% of one clock period.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• KIEE International Transactions on Power Engineering
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• v.12A no.2
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• pp.39-44
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• 2002

This paper proposes some alternatives fur the power system linkage between South and North Korea, under the current situation. Since little information and data on the North-Korean power system are available so far, many efforts have been made to collect the required data for the North system as much as possible if available, and suppose, estimate and/or conjecture many things otherwise. Using these collected or assumed data, the characteristics of bus voltage and power flow are being studied to estimate the feasibility of the proposed linkage alternatives. To this end, many case studies have been made to examine the performance of acceptable interconnection alternatives.

• Journal of Biomedical Engineering Research
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• v.9 no.1
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• pp.79-86
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• 1988

This paper describes the design of a hardware systenl for ECG feature extraction based on pipeline processor consistinsf of three microcomputers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters parameters-heart rate, morPhology, axis, and 57 segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken Loye of one clock period.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.731-733
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• 1988

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.

• KSCI Review
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• v.1 no.2
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• pp.73-94
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• 1995

In this paper, design of efficient NDB(Network Data Base) for the activation plan of chain information network. The DB structure build up, logical structure, store structure, physical structure, the data express for one's record, and the express using linked in the releation of data. Also express as hierarchical model on the DSD(Data Structure Diagram) from the database with logical structure. Each node has express on record type, the linked in course of connective this type, the infuence have efficent of access or search of data, in the design for connection mutually a device of physical, design for database, and construction a form of store for logical. Also activation of chain information network of efficent, using POS(Point Of Sale) system in OSI(Open Systems Interconnection) environment for network standardization, and build up network a design for system.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.642-647
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• 2009

We proposed the method of avionics integrated architecture using high-speed fiber optic bus. Typically, data bus of aircraft consists of electronic and optic data transmission method. Avionics systems are difficult to operate the electronic data transmission method for the high speed data processing, synchronization and interconnection between flight control system and flight management system efficiently. In this paper, it is known to look into the problem of data bus and the advanced trend in avionics systems, and propose the appropriate data bus of the advanced avionics systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.250-260
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• 2023

In this paper, we designed a IoT(Internet of Things) sensor block embedded lightweight house deck structures that can be implemented using Carbon Fiber Reinforced Polymer(CFRP). Deck-Sensor interconnection interface block via IoT connectivity Hub that can mount external environmental sensors such as fire sensors on the Deck body itself was also proposed. Additionally we described the configuration of devices for data acquisition and analysis based on IoT environmental detection sensors that can be commonly installed and used on these deck bodies. On the other hand, received sensing data based monitoring user interface(UI) also developed and used for sensing data analysis for remote monitoring center. Through the implementation of such IoT-based sensor data transmission and collection analysis devices and UI software, this paper confirmed the availability of CFRP based lightweight House deck structure and possibility of CFRP deck-based IoT sensor data networking and analysis functions.