• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.10
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• pp.1312-1318
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• 2020

In this paper, we propose a video transmission scheme for exclusive OR based video streaming (XC) that can improve the efficiency of video streaming by using receivers' caches and coding of video data. Contrary to conventional streaming schemes such as multicast where video contents can be transmitted on single channel only when two clients request the same video, the proposed streaming scheme can transmit video contents on single channel conditionally according to the status of the clients' caches even though two clients request different video contents. We analyze the performance of the proposed transmission for XC in terms of the streaming efficiency through extensive computer simulations and compare it with a conventional scheme. Simulation results show that the proposed scheme can enhance the streaming efficiency by 21%, compared with the conventional scheme.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.77-81
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• 2001

In this paper, a RAID system is modeled and simulated by using the DEVS formalism. The RA[D system interacts with a host system by using the high-speed Fibre channel protocol and stores input data in an array of IDE disks. The DEVS formalism specifies discrete event systems in a hierarchical, modular manner. The RAID system model is composed of three units: primary-PCI unit, secondary-PCI unit and CPU unit. The primary-PCI unit interfaces with the host system and caches I/O data. The secondary-PCI unit includes disks. The CPU unit controls overall system. The control algorithm of CPU and PCI transactions are analyzed and modeled. From an analysis of simulation events, we can conclude that the proposed model satisfies given requirements.

• Journal of the Korea Society for Simulation
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• v.11 no.1
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• pp.11-22
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• 2002

In this paper, a RAID system is modeled and simulated by using the DEVS formalism. The RAID system interacts with a host system by using the high-speed Fibre channel protocol and stores data in an array of IDE disks. The DAVS formalism specifies discrete event systems in a hierarchical, modular manner. The RAID system model is composed of three units: primary-PCI unit, secondary-PCI unit and MCU unit. The primary-PCI unit interfaces with the host system and I/O data caches. The secondary-PCI unit includes disks. The MCU unit controls overall system. The control algorithm of MCU and PCI transactions are analyzed and modeled, From the analysis of simulation events, we can conclude that the proposed model satisfies given requirements.

• Journal of KIISE:Software and Applications
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• v.26 no.9
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• pp.1073-1084
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• 1999

이동 컴퓨팅 환경에서 이동 호스트는 제한된 대역폭을 효율적으로 사용하고 이동 트랜잭션의 응답 시간을 향상시키기 위하여 캐쉬를 이용한다. 그리고 이동 호스트에 캐슁된 데이타가 이동 지구국에서 갱신되면 이동 호스트의 캐쉬 일관성을 유지하기 위하여 이동 지구국은 무효화 메시지를 방송한다. 그러나 이동 지구국에서 주기적으로 무효화 메시지를 방송하는 방법은 이동 트랜잭션의 빠른 처리를 위하여 이동 지구국으로부터 데이타를 즉시 캐슁하는 경우에 이동 트랜잭션의 직렬가능한 수행을 보장할 수 없는 경우가 발생한다. 본 연구에서는 캐슁된 데이타를 이용하여 이동 트랜잭션을 수행하는 경우에 록을 이용하여 이동 트랜잭션의 직렬가능한 수행을 보장하는 UCL-MT 방법과 록 관리 방법을 제안한다. 제안하는 UCL-MT 방법은 이동 트랜잭션을 완료하기 이전에 이동 트랜잭션이 접근한 데이타 정보를 이용하여 지구국에서 사이클을 탐지함으로써 이동 트랜잭션의 직렬가능한 수행을 보장한다. 또한 제안하는 록 관리 방법은 이용할 수 있는 대역폭의 크기에 따른 무효화 메시지 내용의 변화에 유연하게 적용될 수 있다. Abstract In mobile computing environments, a mobile host caches the data to use the narrow bandwidth efficiently and improve the response time of a mobile transaction. If the cached data in mobile host is updated at a mobile support station, the mobile support station broadcasts an invalidation message for maintaining the cache consistency of a mobile host. But when a mobile transaction accesses the data which is not in cache, if a mobile host caches the data immediately from a mobile support station for processing a mobile transaction rapidly, the method that a mobile support station broadcasts an invalidation message periodically, happens to the case that can not guarantee the serializable execution of a mobile transaction. In this paper, we propose the UCL-MT method and lock management method, as a mobile transaction is executed using cached data. Since, using the data a mobile transaction accessed, the UCL-MT method detects a cycle in a mobile support station before the completion of the mobile transaction, it guarantees the serializable execution of the mobile transaction. Also, proposing lock management method can be adapted flexibly at the change of invalidation message content, according to the available bandwidth.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.78-92
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• 1999

In mobile computing environments, to efficiently use the narrow bandwidth of wireless networks a mobile host caches the data that are frequently accessed. To guarantee the correctness of the mobile transaction, the data cached in a mobile host must be consistent with the data in a server. This paper proposes a new strategy which maintains cache consistency efficiently when the data cached in a mobile host are inconsistent with the data in a server by the mobility of the mobile host at the asynchronous mobile environment. In this strategy, the size of the invalidation message is relatively small and is independent of the number of data to be invalidated under conditions of variable update rates/patterns. So this strategy uses the narrow bandwidth of wireless networks efficiently and reduces the communication cost.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.67-78
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• 2016

The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.

• Journal of Information Processing Systems
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• v.17 no.1
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• pp.51-62
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• 2021

On-chip caches of graphics processing units (GPUs) have contributed to improved GPU performance by reducing long memory access latency. However, cache efficiency remains low despite the facts that recent GPUs have considerably mitigated the bottleneck problem of L1 data cache. Although the cache miss rate is a reasonable metric for cache efficiency, it is not necessarily proportional to GPU performance. In this study, we introduce a second key determinant to overcome the problem of predicting the performance gains from L1 data cache based on the assumption that miss rate only is not accurate. The proposed technique estimates the benefits of the cache by measuring the balance between cache efficiency and throughput. The throughput of the cache is predicted based on the warp occupancy information in the warp pool. Then, the warp occupancy is used for a second bypass phase when workloads show an ambiguous miss rate. In our proposed architecture, the L1 data cache is turned off for a long period when the warp occupancy is not high. Our two-level bypassing technique can be applied to recent GPU models and improves the performance by 6% on average compared to the architecture without bypassing. Moreover, it outperforms the conventional bottleneck-based bypassing techniques.

• Journal of Computing Science and Engineering
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• v.9 no.3
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• pp.134-141
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• 2015

In on-demand multimedia streaming systems, streaming techniques are usually combined with proxy caching to obtain better performance. The patch streaming technique has no start-up latency inherent to it, but requires extra bandwidth to deliver the media data in patch streams. This paper proposes a proxy caching technique which aims at reducing the bandwidth cost of the patch streaming technique. The proposed approach determines media prefixes with high patching cost and caches the appropriate media prefix at the proxy/local server. Herein the scheme is evaluated using a synthetically generated media access workload and its performance is compared with that of the popularity and prefix-aware interval caching scheme (the prefix part) and with that of patch streaming with no caching. The bandwidth saving, hit ratio and concurrent number of clients are used to compare the performance, and the proposed scheme is found to perform better for different caching capacities of the proxy server.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.15-22
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• 2017

Although there are many efficient techniques to minimize the speed gap between processor and the memory, it remains a bottleneck for various commercial implementations. Since secondary memory technologies are much slower than main memory, it is challenging to match memory speed to the processor. Usually, hard disk drives include semiconductor caches to improve their performance. A hit in the disk cache eliminates the mechanical seek time and rotational latency. To further improve performance a divided disk cache, subdivided between metadata and data, has been proposed previously. We propose a new algorithm to apply the SSD that is flash memory-based solid state drive by applying FTL. First, this paper evaluates the performance of such a disk cache via simulations using DiskSim. Then, we perform an experiment to evaluate the performance of the proposed algorithm.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.