• Journal of Computing Science and Engineering
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• v.3 no.4
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• pp.195-215
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• 2009

Worst-case execution time (WCET) analysis is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. While significant progress has been made for WCET analysis of instruction caches, the data cache timing analysis, especially for set-associative data caches, is rather limited. This paper proposes an approach to safely and tightly bounding data cache performance by computing the worst-case stack distance of data cache accesses. Our approach can not only be applied to direct-mapped caches, but also be used for set-associative or even fully-associative caches without increasing the complexity of analysis. Moreover, the proposed approach can statically categorize worst-case data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to enhance the worst-case data cache performance. Our evaluation shows that the proposed data cache timing analysis technique can safely and accurately estimate the worst-case data cache performance, and the overestimation as compared to the observed worst-case data cache misses is within 1% on average.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.1-9
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• 2007

Since data caches used in modern embedded processors consume significant fraction of total processor power up to 40%, embedded processors need power-efficient high performance data caches. This paper proposes a prefetching data cache structure which pursuing low power consumption. We added tag history table on existing data cache structure which includes hardware unit for data prefetching so that reduce the number of parallel lookup on tag memory. This strategic cache structure remarkably reduces power consumption for parallel tag lookup. Experimental results show that the proposed cache architecture induce low power consumption while maintain the same cache performance.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.6
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• pp.2078-2094
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• 2015

Now a days, Efficient processing of Broadcast Queries is of critical importance with the ever-increasing deployment and use of mobile technologies. BQs have certain unique characteristics that the traditional spatial query processing in centralized databases does not address. In novel query processing technique, by maintaining high scalability and accuracy, latency is reduced considerably in answering BQs. Novel approach is based on peer-to-peer sharing, which enables us to process queries without delay at a mobile host by using query results cached in its neighboring mobile peers. We design and evaluate cooperative caching techniques to efficiently support data access in ad hoc networks. We first propose two schemes: Cache Data, which caches the data, and Cache Path, which caches the data path. After analyzing the performance of those two schemes, we propose a hybrid approach (Hybrid Cache), which can further improve the performance by taking advantage of Cache Data and Cache Path while avoiding their weaknesses. Cache replacement policies are also studied to further improve the performance. Simulation results show that the proposed schemes can significantly reduce the query delay and message complexity when compared to other caching schemes.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.20-31
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• 2014

Recently, cache sharing methods have been studied in order to effectively reply to user requests in mobile P2P networks. In this paper, we propose a cache sharing scheme based on a cluster considering the peer connectivity in mobile P2P networks. The proposed scheme shares caches by making a cluster that consists of peers preserving the connectivity among them for a long time. The proposed scheme reduces data duplication to efficiently use the cache space in a cluster. The cache space is divided into two parts with a data cache and a temporary cache for a cache space. It is possible to reduce the delay time when the cluster topology is changed or the cache data is replaced utilizing a temporary cache. The proposed scheme checks the caches of peers in a route to a cluster header and the caches of one-hop peers in order to reduce the communication cost. It is shown through performance evaluation that the proposed scheme outperforms the existing schemes.

• Journal of KIISE:Databases
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• v.31 no.5
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• pp.457-467
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• 2004

The efficiency of algorithms managing data caches has a major impact on the performance of systems that utilize client-side data caching. In these systems, two versions of data can be maintained without an additional space overhead of the server by exploiting the replication of data in the server's buffer and clients' caches. In this paper, we present a new cache consistency algorithm employing versions: Two Versions-Callback Locking (2V-CBL). Our experimental results indicate that 2V-CBL provides good performance, particularly outperforms a leading cache consistency algorithm, Asynchronous Avoidance-based Gache Consistency, when some clients run only read-only transactions.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.175-180
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• 2012

In order to overcome the complexity and performance limit problems of superscalar processors, the multicore architecture has been prevalent recently. The configuration and the size of instruction and data caches greatly gives effect on the performance of multicore processors. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the 2-core to 16-core architectures with different sizes of caches extensively. As a result, the 2-way set associative instruction and data cache with the size of 64KB brought the best cost-effective performance.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.191-198
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• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.63-70
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• 2006

This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.