• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.27-33
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• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.191-197
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• 2005

Biped walking is the main feature of a humanoid robot. In a biped walking robot, there are many actuators to be controlled and many sensors to be interfaced. In this paper, we propose a DSP-based controller for a miniature biped walking robot with 21 RC servo motors. The proposed controller has a hierarchical structure; a host PC, a DSP-based main controller, and an auxiliary controller with an FPGA chip. The host PC generates and transmits the robot walking data for given walking parameters such as stride, walking period, etc. The main controller implemented with a TMS320LF2407A controls 21 RC servo motors via the auxiliary controller. We also perform some experiments for balancing motion and walking on a slope terrain with interfacing a 2-axis acceleration sensor and a TMS320LF2407A.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2882-2884
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• 2005

본 논문에서는 인터넷을 통한 멀티미디어 스트리밍 서비스 환경에서 다양한 표준으로 압축된 컨텐츠의 디코딩을 지원하기 위하여 general purpose DSP (Digital Signal Processor) 기반의 멀티미디어 서비스 플랫폼을 구현하였다. 다양한 표준 방식으로 압축된 멀티미디어 컨텐츠를 재생하기 위하여 Host 프로세서와 DSP 구조의 하드웨어를 설계하고, 멀티미디어 코덱을 DSP에 다운로드하는 소프트웨어적인 기법을 적용하였다. 설계한 플랫폼의 동작을 검증하기 위하여 리눅스 기반에서 DSP를 제어하는 네트워크 클라이언트 소프트웨어를 구현하고, Tl의 TMS 320C6416을 대상으로 구현한 MPEG-2 비디오와 AC-3 오디오 코덱을 적용하여 스트리밍 환경에서 멀티미디어 데이터가 원활하게 재생되는 것을 보였다.

• Speech Sciences
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• v.7 no.2
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• pp.225-234
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(Code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56362. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.264-267
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• 2003

The stereoscopic vision robot system design with DSP processor is presented. The vision system is consists of control system, vision system and host computer. The vision system is based on 32bits DSP processor. The stereoscopic image processing applies the correlation coefficient method to execute the software. The result of experiment, image recognition rate is 95% on the stereoscopic vision robot system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.205-208
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• 2002

The stand-alone transmission system design on compressed still image using DSP processor and Wavelet is presented. The target system is based on 32bits DSP processor. The image is compressed with Wavelet. The system for NTSC format image signal is able to transmit still image data to be high speed and is applicable to a surveillance and inspection system independently.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.38-46
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• 1999

Spindle motor current is used to estimate the cutting force indirectly and control the feed rate for the cutting force regulation. The proposed algorithm is implemented to a DSP board based hardware for the industrial application. The software to make POP terminal communicate with the DSP board and POP server is coded under Windows 95 environment. Experiments under varying cutting conditions show that the DSP board recognizes the information of installed cutting tool and cutting conditions delivered from the POP server to use them for the proper control of the feed rate. The cutting force is regulated well during machining of tapered or stepped workpiece and circular shaped workpiece as well.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.38-49
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• 1998

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed for real-time or high-speed(faster than real-time) simulators. This paper presents an enhanced strategy in which high computing power can be provided by parallel processing of DSP processors with communication links. DSP system is designed for general purpose. Parallel DSP system can be easily expanded by just connecting new DSP modules to the system. General urpose DSP modules and a VME interface module was developed. New model and techniques for the task allocation are also presented which take into account the special characteristics of parallel I/O and computation. As a realistic cost function of task allocation, we suggested 'simulation period' which represents the period of simulation output intervals. Based on the development of parallel DSP system and realistic task allocation techniques, we cound achieve good efficiency of parallel processing and faster simulation speed than real-time.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2681-2683
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• 2003

본 논문에서는 HDTV(High Definition TV) 방송수신을 위한 DSP기반의 HD급 비디오/오디오 디코더 시스템을 개발하고 그 성능을 확인하였다. DSP 플랫폼은 TI사의 TMS320C6415를 대상으로 하였으며 TI의 DSP RTOS인 DSP/BIOS를 이용하여 방송스트림인 TS (Transport Stream)을 분리하기 위한 TS Demuxer, MPEC-2 비디오 디코더 및 AC-3 오디오 디코더 알고리즘을 통합하였으며, 각각의 알고리즘은 대상 DSP 플랫폼인 TMS320C64x에 맞게 고정소수점 구조화 및 최적화를 실시하였다. 테스트를 위한 시스템은 스트리밍을 위한 호스트 PC와 PCI버스를 통해 연결된 DSP보드로 구성하였으며 실제 HDTV방송용 스트림과 SD급 스트림을 이용하여 성능을 확인하였다.