• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Journal of Aerospace System Engineering
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• v.17 no.2
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• pp.45-55
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• 2023

This study conducted aeromechanics modeling and structural load analyses of Tilt Rotor Aeroacoustic Model (TRAM), a 25% scaled V-22 tiltrotor model used in wind tunnel tests. A rotorcraft comprehensive analysis code, CAMRAD II, was used. Analysis results of this study in low-speed forward flights were compared with DNW test and previous analysis results. Blade flap bending moments were in good agreement with measured data. Mean values and oscillatory loads for lead-lag bending and torsion moments were slightly different from measured data. However, when mean values were removed, results of structural loads for one rotor revolution were moderately compared with wind tunnel tests and previous analyses. Total forces and half peak-to-peak forces of the pitch link reasonably well matched with previous analysis results and measured data. Finally, harmonic magnitudes of blade structural loads were investigated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1814-1819
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• 1996

This paper describes a dnw serial interface system which uses comma free code. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3VTR and HDTV Receiver.The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are requeired. This serial data trasfer technique is possible the error detection and the self synchronization, also easy edge insertion for PLL control. It is also cost effective because is does not requeire RF PLL, scrambling, and NRZI hardware.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.7
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• pp.268-277
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• 1999

In order to make an advanced dry-friction engineering material, wax-impregnated nylons were synthesized by anionic polymerization of $\varepsilon$-caprolactam in the presence of apraffin wax. DNX-125S, which has lowest melting point among four different kinds of waxs investigated, showed excellent miscibiility with $\varepsilon$-carprolactam and no effect on the polymerization reaction. Five different kinds of wax-impregnated nylons from of DNW-125S content 0% to 8% were synthesized and tested. Among the samples, wax-free nylon has the highest yield and tensile strength and hardness, while the specimen with2% wax has the largest elongationi and energy absorption to break. The wax-impregnated nylon with a wax content 6% showdd the smallest friction coefficient under slow sliding speed and low load. Bus as the sliding speeds were increased to high, thespcieimen with 8% wax has better friction property.

• Korean Journal of Environmental Biology
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• v.37 no.2
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• pp.136-143
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• 2019

This study investigates the effect of denitrified biofloc water on changes in the water quality parameters and the physiological characteristics of shrimps. Biofloc rearing water contains a large number of microorganisms and can rapidly stabilize the water quality and energy saving if reusable due to high water temperatures. Rearing water contain floating bacteria with both aerobic and anaerobic bacteria. Therefore, when the carbon source is added in limited air supply, the anaerobic state is activated and the denitrification process is possible. In this study, the denitrification water had the following properties: ammonia (6.9 mg L^-1), nitrite (0.3 mg L^-1), nitrate concentration (9.2 mg L^-1), high pH (8.42) and alkalinity (590 mg L^-1). The experimental group consisted of seawater (SW, control), a mixture of Seawater and denitrified biofloc water (DNW) in the ratio of 3:1, 1:1 and DNW only. All experiments were done in triplicate. As a result, the survival rate never changed even when 100% of the denitrification water was utilized. However, a body fluid analysis showed that creatine and BUN were increased due to index of stress and the tissue damage resulting from the high denitrified water content. Body fluid ions (Na⁺, K⁺, and Cl^-) significantly decreased as the denitrified water content increased. It was recommended that the denitrification water be mixed with a certain ratio (less than 50%) in the future as it may affect the osmotic pressure control in shrimps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.306-316
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• 2016

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.