• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• Transactions on Semiconductor Engineering
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• v.2 no.2
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• pp.10-14
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• 2024

This paper presents a circuit design aimed at generating the required reference voltage and temperature sensor voltage in conjunction with an ADC, utilizing the current generated by temperature characteristics of BJT components for sensor data conversion. Additionally, two control methods are introduced to reduce the standard deviation of the circuit, resulting in over a ten-fold decrease in standard deviation. The proposed circuit occupies an area of 0.057mm² and was implemented using 55nm RF process.