• ETRI Journal
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• v.31 no.5
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.119-122
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• 2000

Recently, many complex DSP (Digital Signal Processing) algorithms have being realized on RISC CPU due to good compilation, low power consumption and large memory space. But, real-time implementation of multiple DSP algorithms on RISC requires the minimum and efficient memory usage and the lower occupancy of CPU. In this thesis, the original floating-point code of MPEG-1 audio decoder is converted to the fixed-point code and then optimized to the efficient assembly code in time-consuming function in accord with RISC feature. Finally, compared with floating-point and fixed-point, about 30 and 3 times speed enhancements are achieved respectively. And 3~4 times memory spaces are spared.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.205-208
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• 2000

In this paper, we have designed a pager based on the FLEX protocol. The pager consists of a decoder, a MCU, a SPI, and a User interface. The decoder contains the following blocks： synchronizer, de-interleaver, error corrector, packet builder. The decoded data is converted to SPI packets for communication between the MCU and the FLEX decoder. The host MCU is a RISC pipelined architecture, so it processes data at high speed and also sends messages to user interface. We have designed the proposed pager as structural modeling using VHDL language. Then, We simulated and synthesized it using tool of SYNOPSYS corporation.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.51-54
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• 2004

In this paper, we analyze the performance of LDPC decoder for DVB-S2 system. The performance analysis is performed by computer simulations based on AWGN channel and high order modulation technique including 16APSK and 32APSK. For normal frame codeword length N = 64800, the performance of LDPC decoder is only away 0.7dB to 1dB from Shannon limit with respect to each modulation. The constructions and encoding process of LDPC codes which are used for DVB-S2 system are also presented and described.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.431-434
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• 2004

In this paper we present about implementation of channel coder and Viterbi decoder for Mobile communication & IEEE 802.11a Wireless LAN. In the IEEE 802.11a Wireless LAN decoding provided that Viterbi algorithm and convolutional encoder by constraint k=7, ($133_8,\;171_8$) for channel error correction. This Paper presents a novel survivor memory management and decoding techniques with sequential backward state transition control in the trace-back Viterbi decoder, In order to verification we provide to the examples of circuit design and decoding results.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.251-253
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• 2008

최근 유럽에서 DVB-T HDTV 방송 표준이 정하지면서 오디오 포맷으로 HE-AAC가 채택되었다. HE-AAC는 압축효율은 높지만 연산량이 높아 낮은 성능의 DSP에서 수행하기에는 어려움이 있다. DVB-T에서는 5.1채널을 사용하고 있어 더욱더 많은 연산을 필요로 한다. 본 논문은 ISO/DEC 14496-3 MPEG4 HE(High Efficiency)-AAC의 Level4에 해당하는 Multichannel Decoder를 최적화하여 구현하고. 가장 많은 연산을 필요로 하는 Synthesis Filter Bank에 제안된 알고리즘을 적용하여 연산량을 줄였고 대부분의 연산부를 어셈블리로 코드 최적화를 하여 작은 성능의 DSP를 사용하여 실시간 Multichannel HE-AAC Audio Decoder의 구현이 가능하게 하였다. DVB-T 오디오 시스템에 필수로 필요한 Audio Description, Dynamic Range Control, Downmix 등을 함께 구현하여 실제 수신기에 사용이 가능하도록 하였다. DSP는 Samsung의 CalmRISC16 + MAC24 core 를 사용하였다.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.298-300
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• 2004

In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.183-186
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• 1998

In this article, an algorithm for improving the performance of the convolutional decoder for a COFDM receiver using the subchannel information is introduced. The proposed algorithm defines the average amplitude of the received signal at each subchannel as a certainty of the received signal at that subchannel. If the certainty of a subchannel is low, then the received signal of that subchannel is mitigated, and the brach matric of the convolutional decoder is affected by that signal in a relatively small degree. However if the certainty of a subchannel is high, then the signal is enlarged and the branch matric is affected in a relatively large degree. simulations will show the improved BER performance of a COFDM system when the proposed method has been applied.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.679-682
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• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.