• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

• Journal of the Korea Society of Computer and Information
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• v.19 no.5
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• pp.43-52
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• 2014

In this paper, we propose Gravity Removal and Vector Rotation algorithm for counting steps of wearable device, and we evaluated the proposed GRVR algorithm with Micro-Electro-Mechanical (MEMS) 3-axis accelerometer equipped in low-power wearable device while the device is mounted on various positions of a walking or running person. By applying low-pass filter, the gravity elements are canceled from acceleration on each axis of yaw, pitch and roll. In addition to DC-bias removal and the low-pass filtering, the proposed GRVR calculates acceleration only on the yaw-axis while a person is walking or running thus we count the step even if the wearable device's axis are rotated during walking or running. The experimental result shows 99.4% accuracies for the cases where the wearable device is mounted in the middle and on the right of the belt, and 91.1% accuracy which is more accurate than 83% of commercial 3-axis pedometer when worn on wrist for the case of axis-rotation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.545-549
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• 2010

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

• Korean Journal of Optics and Photonics
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• v.2 no.3
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• pp.139-148
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• 1991

A fiber-optic magnetic sensor system for the detection of small ac magnetic field(200Hz-2 kHz) was constructed. Magnetic field sensing part was fabricated by bonding a section of optical fiber to amorphous metallic glass(2605SC) having large magnetostriction effect. And with the directional coupler, all fiber type Mach-Zehnder interferometer was constructed to measure the variation of the external magnetic field by translating it into the optical phase shift in the interferometer. The signal fading problem of the interferometer, which is due to random phase drifts originated from the environment, i.e., temperature fluctuation, vibrations, etc., was elliminated by feedback phase compensation. This allows the sensitivity to be maintained at the maximum by keeping the interferometer in quadrature phase condition. The frequency response of metallic glass was found to be nearly flat in the range of 90 Hz-2 kHz and dc bias field for the maximum ac response was 3.5 Oe. The interferometer output showed good linearity over the range $\pm$0.5 Oe. For 1 kHz ac magnetic field the scale factor S and the minimum detectable magnetic field were measured to be 8.0 rad/Oe and $3X10^{-6} Oe/\sqrt{Hz}$at 1 Hz detection bandwidth respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.388-388
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• 2016

Chemical mist deposition (CMD) of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) was investigated with cavitation frequency f, solvent, flow rate of nitrogen, substrate temperature $T_s$, and substrate dc bias $V_s$ as variables for efficient PEDOT:PSS/crystalline (c-)Si heterojunction solar cells (Fig. 1). The high-speed camera and differential mobility analysis characterizations revealed that average size and flux of PEDOT:PSS mist depend on f, solvent, and $V_s$. The size distribution of mist particles including EG/DI water cosolvent is also shown at three different $V_s$ of 0, 1.5, and 5 kV for a f of 3 MHz (Fig. 2). The size distribution of EG/DI water mist without PEDOT:PSS is also shown at the bottom. A peak maximum shifted from 300-350 to 20-30 nm with a narrow band width of ~150 nm for PEDOT:PSS solution, whose maximum number density increased significantly up to 8000/cc with increasing $V_s$. On the other hand, for EG/water cosolvent mist alone, the peak maximum was observed at a 72.3 nm with a number density of ~700/cc and a band width of ~160 nm and it decreased markedly with increasing $V_s$. These findings were not observed for PEDOT:PSS/EG/DI water mist. In addition, the Mie scattering image of PEDOT:PSS mist under white bias light was not observed at $V_s$ above 5 kV, because the average size of mist became smaller. These results imply that most of solvent is solvated in PEDOT:PSS molecule and/or solvent is vaporized. Thus, higher f and $V_s$ generate preferentially fine mist particle with a narrower band width. Film deposition occurred when $V_s$ was impressed on positive to a c-Si substrate at a Ts of $30-40^{\circ}C$, whereas no deposition of films occurred on negative, implying that negatively charged mist mainly provide the film deposition. The uniform deposition of PEDOT:PSS films occurred on textured c-Si(100) substrate by adjusting $T_s$ and $V_s$. The adhesion of CMD PEDOT:PSS to c-Si enhanced by $V_s$ conspicuously compared to that of spin-coated film. The CMD PEDOT:PSS/c-Si solar cell devices on textured c-Si(100) exhibited a ${\eta}$ of 11.0% with the better uniformity of the solar cell parameters. Furthermore, ${\eta}$ increased to 12.5% with a $J_{sc}$ of $35.6mA/cm^2$, a $V_{oc}$ of 0.53 V, and a FF of 0.67 with an antireflection (AR) coating layer of 20-nm-thick CMD molybdenum oxide $MoO_x$ (n= 2.1) using negatively charged mist of 0.1 wt% 12 Molybdo (VI) phosphoric acid n-Hydrate) $H_3(PMo_{12}O_40){\cdot}nH_2O$ in methanol. CMD. These findings suggest that the CMD with negatively charged mist has a great potential for the uniform deposition of organic and inorganic on textured c-Si substrate by adjusting $T_s$ and $V_s$.

• Korean Journal of Materials Research
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• v.5 no.6
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• pp.754-762
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• 1995

Strontium titanate(SrTiO$_3$) thin film was prepared on Si substrates by RF magnetron sputtering for a high capacitance density required for the next generation of LSTs. The optimum deposition conditions for SrTiO$_3$thin film were investigated by controlling the deposition parameters. The crystallinity of films and the interface reactions between SrTO$_3$film and Si substrate were characterized by XRD and AES respectively. High quality films were obtained by using the mixed gas of Ar and $O_2$for sputtering. The films were deposited at various bias voltages to obtain the optimum conditions for a high quality file. The best crystallinity was obtained at film thickness of 300nm with the sputtering gas of Ar+20% $O_2$and the bias voltage of 100V. The barrier layer of Pt(100nm)/Ti(50nm) was very effective in avoiding the formation of SiO$_2$layer at the interface between SrTiO$_3$film and Si substrate. The capacitor with Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si structure was prepared to measure the electric and the dielectric properties. The highest capacitance and the lowest leakage current density were obtained by annealing at $600^{\circ}C$ for 2hrs. The typical specific capacitance was 6.4fF/$\textrm{cm}^2$, the relative dielectric constant was 217, and the leakage current density was about 2.0$\times$10$^{-8}$ A/$\textrm{cm}^2$ at the SrTiO$_3$film with the thickness of 300nm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.