• Environmental and Resource Economics Review
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• v.21 no.3
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• pp.493-517
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• 2012

This paper analyzes a price discovery process for gasoline among branded and independent stations in Korea using a vector error correction model (VECM) and directed acyclic graphs (DAG). Two data sets for daily prices of medium level gasoline running from April 15, 2008 to May 31, 2009 and from January 1, 2011 to December 31, 2011 are used for empirical analysis. Empirical results show that S-OIL has an exogeneity and played a important role in the flow of price information in the market in the first period. In the second period, SK energy played a key role in price discovery process in the market. The price of NH-OIL stations do not cause the price of any other stations, which implies that the entrance of new branded stations with lower gasoline price to market has no influence on gasoline prices of retail markets.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.163-170
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• 2006

Most scheduling problems including DAG(Directed Acyclic Graph)-based are known to be NP-complete, so many heuristic-based scheduling algorithms have been researched. HEFT and CPOP are such algorithms which have been devised to be effective in heterogeneous environment. We proposed, in the previous research, three scheduling algorithms which are effective in realistic global heterogeneous environment: CPOC, eCPOPC and eCPOP. In this paper, the heuristics which are used in the above five algorithms will be systematically analyzed. Those algorithms will be also studied experimentally using various benchmarks. Experimental results show that the eCPOC generates better schedules than any other algorithms and the heuristics which are used in the proposed algorithms are effective in the global heterogeneous environment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.591-593
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• 2022

This paper proposes a partial offloading system for minimizing application service processing latency in an FEC (Fog/Edge Computing) environment, and it analyzes the offloading effect of the proposed system against local-only and edge-server-only processing based on network load. A partial offloading algorithm based on reconstruction linearization of multi-branch structures is included in the proposed system, as is an optimal collaboration algorithm between mobile devices and edge servers [1,2]. The experiment was conducted by applying layer scheduling to a logical CNN model with a DAG topology. When compared to local or edge-only executions, experimental results show that the proposed system always provides efficient task processing strategies and processing latency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Proceedings of the Korean Society of Postharvest Science and Technology of Agricultural Products Conference
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• 2006.11a
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• pp.117-127
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• 2006

• Bulletin of the Korean Chemical Society
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• v.8 no.5
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• pp.434-435
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• 1987

• Bulletin of the Korean Chemical Society
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• v.18 no.10
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• pp.1115-1117
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• 1997

• Bulletin of the Korean Chemical Society
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• v.18 no.12
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• pp.1240-1242
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• 1997

• Bulletin of the Korean Chemical Society
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• v.16 no.2
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• pp.191-193
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• 1995