• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.709-712
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• 2012

In this paper, current-voltage have been considered for DGMOSFET, using the analytical model. The Possion equation is used to analytical. Threshold voltage is defined as top gate voltage when drain current is $10^{-7}A$. Investigated current-voltage characteristics of channel length changed length of channel from 20nm to 100nm. Also, The changes of current-voltage have been investigated for various channel thickness and doping concentration using this model, given that these parameters are very important in design of DGMOSFET. The deviation of conduction path and the influence of conduction path on current-voltage have been considered according to the dimensional parameters of DGMOSFET.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.269-275
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• 1988

In this paper, a high efficiency motor drive system which improves the multi-step response of PM step motors by reducing the transition time of the motor drive current, is studied by designing a dual-voltage drive circuit. The designed drive circuit eventually prevents the motor from decreasing drive torque while the stepping rate is increased. The method of designing a dual-voltage drive circuit with the motor specifications is suggested in order to improve the response of step rate and drive efficiency. Also, despite improving the power efficiency on motor driving, the response characterstics suggested by the motor manufacture's specifications are satisfied without any special deficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.