• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.533-539
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• 2018

In this paper, the transformer type superconducting fault current limiter (SFCL) with additionally coupled circuit was suggested and its peak fault current limiting characteristics due to the fault condition to affect the fault current were analyzed through the fault current limiting tests. The suggested transformer type SFCL is basically identical to the previous transformer type SFCL except for the additional coupled circuit. The additional coupled circuit, which consists of the magnetically coupled winding to the primary and the secondary windings together with another superconducting element and is connected in parallel with the secondary winding of the transformer type SFCL, is contributed to the peak fault current limiting operation for the larger transient fault current directly after the fault occurrence. To confirm the fault current limiting operation of the suggested SFCL, the fault current limiting tests of the suggested SFCL were performed and its effective peak fault current limiting characteristics were analyzed through the analysis on the electrical equivalent circuit.

• Journal of Welding and Joining
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• v.23 no.5
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• pp.14-19
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• 2005

In high speed $CO_2$ welding, it has been blown to produce no sound bead with undercut or humping bead. In this study welding phenomena through synchronized high speed camera and output welding voltage and current waveform has been analyzed. For the purpose to improve a welding bead, effect of short circuit current rise slope has been examined. With commercial power source it was produced no sound bead by instantaneous short circuit, long arc period and stubbing at welding speed 2.5mm/min Humping bead or undercut were showed by instantaneous short circuit and long arc period. Also, the weld bead was not formed during the long short circuit period after stubbing start and long arc extinguishment period after wire sticking by failure of arc regeneration, because the droplet was not transferred to weld pool. With increasing short circuit current rise slope the frequency of stubbing was decreased and the normal short circuit rate was increased. A control of short circuit current rise slope was effective factor in high speed welding.

• Progress in Superconductivity and Cryogenics
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• v.21 no.4
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• pp.39-43
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• 2019

The breaking of a circuit in DC grid could pose a challenge because of the absence of zero-crossing instant for both current and voltage when a fault occurs. An additional fault current limiting function will be very helpful for reducing the burden of the DC circuit breaker by limiting the fault current to a reasonable value. In this paper, we studied the overcurrent characteristics of several HTS conductors so that we could use the selected conductors for the basic design work of a resistive type fault current limiting module as a part of the circuit breaking system. According to the short-circuit test results, we suggested and compared two different basic design parameters of the HTS fault current limiting module, which will be connected in series to the DC circuit breaker.

• Journal of Information Display
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• v.3 no.3
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

• Journal of Advanced Marine Engineering and Technology
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• v.6 no.1
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• pp.25-33
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• 1982

The characteristics of the stator current and torque of a small three- phase squirrel cage induction motor and studied experimentally under the situation of a single-phase operation due to various causes. Through the experiments, the torque-slip and current-slip curve of single-phase circuit as well as three-phase circuit are obtained and the needed constants are determined. The stator current and torque are calculated by the current and torque equations derived by the unbalanced circuit theory. The numerical values obtained from the above methods are compared with the experimental values under the same conditions. The results of the study are summerized as follow; 1) The values computed by the unbalanced circuit theory generally come to approach the values recorded through experiments. 2) Near the rated load, speed drop is less than 1.2 per cent of the speed of three-phase induction motor and torque reduces less than 3 per cent of it of three-phase induction motor when three-phase induction motor is run under a single-phase. On the other hand, the stator current in a single-phase circuit is more than 1.9 times of it in three-phase circuit. 3) The stalling torque in a single-phase circuit is reduced to about 41 per cent of it in three-phase circuit while the corresponding slip is moved toward the synchroneous speed and the corresponding stator current is increased.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.7
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• pp.331-337
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• 2001

With the increasing reliability of analysis schemes and the dramatically increased calculating speed, the computer simulation has become and indispensable process to predict the interruption capacity of circuit breakers. Generally, circuit breakers have to possess both the small current and large current interruption abilities and the circuit breaker designers need to evaluate its capacities to save the time and the expense. The analysis of small current and the large current interruption performances have been considered separately because the phenomena occurring in a interrupter are quite different. To analyze the dielectric recovery after large current interruption many physical phenomena such as heat transfer, convection and arc radiation, the nozzle ablation, the ionization of high temperature SF(sub)6 gas, the electric and themagnetic forces and so forth mush be considered. However, in the analysis of small current interruption performance only the cold gas flow analysis needs to be carried out because the capacitive current is to small that the influence from the current can be neglected. In this paper, an empirical equation which is obtained from a series of tests to estimate the dielectric recovery strength has been applied to a real circuit breaker. The results of analysis have been compared with the test results and the reliability has been investigated.

• Progress in Superconductivity and Cryogenics
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• v.23 no.2
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• pp.19-23
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• 2021

We have studied the breaking system that combines a resistive superconducting fault current limiter (SFCL) and a DC circuit breaker for DC fault current. To verify the design of the 15 kV DC SFCL, which was driven from the previous work, a 500 V DC system was built and a scale-down SFCL were manufactured. The manufactured SFCL module was designed as a bifilar coil which is a structure that minimizes inductive reactance. The manufactured SFCL module has been experiment to verify characteristics of the current-limiting performance in the DC 500 V system. Also, the manufactured FCL module was combined with the DC circuit breaker to be experimented to analyze the breaking performance. As a result of the experiment, when SFCL was combined to the DC circuit breaker, the energy dissipation received by the DC circuit breaker was reduced by up to 84% compared to when the DC circuit breaker operates alone. We are preparing methods and experiments for the optimal method for much higher performance as a future work.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.4
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• pp.339-347
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• 2022

This study proposes the mitigation method for overcurrent and oscillation motor current in an active short-circuit operation. This operation is attracting attention as the safe state of electric vehicle traction inverters. However, the active short-circuit operation generates oscillation and overcurrent of motor currents during a transient state. The proposed method uses two different safe states in PMSM, such as active short circuit and freewheeling. The active short circuit is used for safe state in a steady state. To reduce the overshoot and oscillation, a freewheeling state is injected between active short-circuit operation by comparing the motor phase current with an analytically calculated steady-state motor current. Freewheeling state is only used in a transient state. The performance is demonstrated through simulations and experimental results. The peak current of the motor was reduced from 52 A to 40 A, and oscillation time was reduced.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1789-1794
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• 2014

This paper suggests an application method for a superconducting fault current limiter (SFCL) using an evaluation index to estimate the risk regarding the short-circuit capacity of the circuit breaker (CB). Recently, power distribution systems have become more complex to ensure that supply continuously keeps pace with the growth of demand. However, the mesh or loop network power systems suffer from a problem in which the fault current exceeds the short-circuit capacity of the CBs when a fault occurs. Most case studies on the application of the SFCL have focused on its development and performance in limiting fault current. In this study, an analysis of the application method of an SFCL considering the risk of the CB's short-circuit capacitor was carried out in situations when a fault occurs in a loop network power system, where each line connected with the fault point carries a different current that is above or below the short-circuit capacitor of the CB. A loop network power system using PSCAD/EMTDC was modeled to investigate the risk ratio of the CB and the effect of the SFCL on the reduction of fault current through various case studies. Through the risk evaluations of the simulation results, the estimation of the risk ratio is adequate to apply the SFCL and demonstrate the fault current limiting effect.