• Transactions on Electrical and Electronic Materials
• /
• v.7 no.4
• /
• pp.167-172
• /
• 2006

Submicron colloidal silica coated with ceria were prepared by mixing of silica and nano ceria particles and modified by hydrothermal reaction. The polishing efficiency of the ceria coated silica slurry was tested over oxide film on silicon wafer. By changing the polishing pressure in the range of $140{\sim}420g/cm^2$ with the ceria coated silica slurries in $100{\sim}300nm$, rates, WIWNU and friction force were measured. The removal rate was in the order of 200, 100, and 300 nm size silica coated with ceria. It was known that the smaller particle size gives the higher removal rate with higher contact area in Cu slurry. In the case of oxide film, the indentation volume as well as contact area gives effect on the removal rate depending on the size of abrasives. The indentation volume increase with the size of abrasive particles, which results to higher removal rate. The highest removal rate in 200 nm silica core coated with ceria is discussed as proper combination of indentation and contact area effect.

• Proceedings of the KAIS Fall Conference
• /
• 2001.05a
• /
• pp.124-128
• /
• 2001

A present semiconductor cleaning technology is based upon RCA cleaning technology which consumes vast amounts of chemicals and ultra pure water(UPW) and is the high temperature Process. Therefore, this technology gives rise to the many environmental issues, and some alternatives such as functional water cleaning are being studied. The electrolyzed water was generated by an electrolysis system which consists of anode, cathode, and middle chambers. Oxidative water and reductive water were obtained in anode and cathode chambers, respectively. In case of NH$_4$Cl electrolyte, the oxidation-reduction potential and pH for anode water(AW) and cathode water(CW) were measured to be +1050mV and 4.8, and -750mV and 10.0, respectively. AW and CW were deteriorated after electrolyzed, but maintained their characteristics for more than 40 minutes sufficiently enough for cleaning. Their deterioration was correlated with CO$_2$ concentration changes dissolved from air. It was known that AW was effective for Cu removal, while CW was more effective for Fe removal. The particle distributions after various particle removal processes maintained the same pattern. In this work, RCA consumed about 9$\ell$chemicals, while EW did only 400$m\ell$ HCI electrolyte or 600$m\ell$ NH$_4$Cl electrolyte. It was hence concluded that EW cleaning technology would be very effective for eliminating environment, safety, and health(ESH) issues in the next generation semiconductor manufacturing.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korean Ceramic Society
• /
• v.36 no.2
• /
• pp.203-209
• /
• 1999

LaAlO3d single phase used as the butter layer on Si wafer for YBa2Cu3O7-$\delta$ superconductor application were prepared by solid state reaction method and by self-sustaining combustion process. The microstructure and crystallity of synthesiszed LaAlO3 powder studied using scanning electron microscope (SEM) and X-ray diffractometer(XRD), specific surface area and sintering characteristics fo powder were investigated by Brunauer-Emmett-Teller (BET) method and dilatometer respectively. In solid state reaction method, it is difficult to obtain LaAlO3 single phase up to 150$0^{\circ}C$ period. However, in self-sustaining combustion process, it is to easy to do it only $650^{\circ}C$. Based on the results of analysis of dilatometer it is easier to obtain high sintering density (98.87%) in self-sustaining combustion process than in the solid state reaction method. This reason is that the average particle size prepared by self-sustaining combustion process is nano crystal size and has high specific surface are value(56.54 $m^2$/g) compared with that by solid state reaction method. Also, LaAlO3 layer on the Si wafer has been achieved by screen printing and sintering method. Even though the sintering temperature is 130$0^{\circ}C$, the phenomena of silicon out diffusion in LaAlO3/Si interphase are not observed.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.1
• /
• pp.33-38
• /
• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.6
• /
• pp.80-85
• /
• 2019

Vanadium dioxide is a well-known metal-insulator phase transition material. Lots of researches of vanadium redox flow batteries have been researched as large scale energy storage system. In this study, vanadium oxide($VO_x$) thin films were applied to cathode for lithium ion battery. The $VO_x$ thin films were deposited on Si substrate($SiO_2$ layer of 300 nm thickness was formed on Si wafer via thermal oxidation process), quartz substrate by RF magnetron sputter system for 60 minutes at $500^{\circ}C$ with different RF powers. The surface morphology of as-deposited $VO_x$ thin films was characterized by field-emission scanning electron microscopy. The crystallographic property was confirmed by Raman spectroscopy. The optical properties were characterized by UV-visible spectrophotometer. The coin cell lithium-ion battery of CR2032 was fabricated with cathode material of $VO_x$ thin films on Cu foil. Electrochemical property of the coin cell was investigated by electrochemical analyzer. As the results, as increased of RF power, grain size of as-deposited $VO_x$ thin films was increased. As-deposited thin films exhibit $VO_2$ phase with RF power of 200 W above. The transmittance of as-deposited $VO_x$ films exhibits different values for different crystalline phase. The cyclic performance of $VO_x$ films exhibits higher values for large surface area and mixed crystalline phase.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.49 no.2
• /
• pp.107-112
• /
• 2000

$(Sr_{0.85}Ca_{0.15})TiO_3$(SCT) thin films were deposited on Pt-coated $TiO_2/SiO_2/Si$ wafer by the rf sputtering method. Experiments were conducted to investigate the electrical properties of SCT thin films with various top electrodes. Various top electrodes as Pt, Al, Ag, Cu were deposited on SCT thin films by sputter and thermal evaporator. The characteristics of C-F and C-V of SCT thin films were not obviously varied with various top electrodes, SCT thin films annealed at $600^{\circ}C$ represents as favorable capacitance characteristics than SCT thin films not annealed, and Pt top electrode have the most high capacitance. The characteristic of I-V of SCT thin films showed that Pt top electrode revealed more less leakage current density than other electrodes, had a leakage current density below 10-8$[A/cm^2]$ until 25[V] applied voltage.

• Journal of the Korean Ceramic Society
• /
• v.43 no.11 s.294
• /
• pp.715-723
• /
• 2006

Perovskite oxide materials are very important for the electronics industry, because they exhibit promising properties. With an interest in the obvious applications, significant effort has been invested in the growth of highly crystalline epitaxial perovskite oxide thin films in our laboratory. And the desired structure of films was formed to achieve excellent properties. $Y_1Ba_2Cu_3O_{7-x}$ (YBCO) superconducting thin films were simultaneously deposited on both sides of 3 inch wafer by inverted cylindrical sputtering. Values of microwave surface resistance R$_2$ (75 K, 145 GHz, 0 T) smaller than 100 m$\Omega$ were reached over the whole area of YBCO thin films by pre-seeded a self-template layer. For implementation of voltage tunable high-quality varactor, A tri-layer structured SrTiO$_3$ (STO) thin films with different tetragonal distortion degree was prepared in order to simultaneously achieve a large relative capacitance change and a small dielectric loss. Highly a-axis textured $Ba_{0.65}Sr_{0.35}TiO_3$ (BST65/35) thin films was grown on Pt/Ti/SiO$_2$/Si substrate for monolithic bolometers by introducing $Ba_{0.65}Sr_{0.35}RuO_3$ (BSR65/35) thin films as buffer layer. With the buffer layer, the leakage current density of BST65/35 thin films were greatly reduced, and the pyroelectric coefficient of $7.6\times10_{-7}$ C $cm^{-2}$ $K^{-1}$ was achieved at 6 V/$\mu$m bias and room temperature.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.05a
• /
• pp.150-150
• /
• 2012

본 연구는 1차원 나노 구조의 합성과 기초적 분석에 관한 연구로써 특히 무기 산화물 나노재료를 그 대상으로 하였다. 내용으로는 첫째, 1차원 코어 나노와이어의 합성을 하였고 Thermal evaporation, substrate의 가열, 그리고 MOCVD 를 사용한 결과들을 나열한다. 둘째, 코어-쉘 나노와이어를 제작하기 위하여 특히 쉘층의 제작방법을 연구하였는데 PECVD, ALD, 그리고 sputtering에 의한 결과들을 나열하고 간단히 설명한다. Thermal evaporation에 의한 1차원 나노와이어 합성의 경우는 MgO의 예를 들었는데 MgO 나노와이어는 Au가 증착된 기판을 열처리하여 Au dot를 형성하고 이의 morphology를 조절하여 최적의 나노와이어 합성조건을 선정하였다. 이로써 기판 morphology가 나노선의 성장및 형상에 영향을 준다는 사실을 알게 되었다. 이 사실은 In2O3기판을 사용하고 이의 표면거칠기를 열처리로 조절하므로써 역시 나노와이어의 성장을 촉진하는 방법을 찾아내었다. 또한 thermal evaporation공법은 source분말의 선택에 따라 다양한 소재를 제작가능하다는 결과를 제시하였다. 예를 들면 SiOx 층이 precoating된 chamber내에서 MgO 나노선을 합성하는 것과 동일한 조건으로 실험을 진행하면 Mg2SiO4 나노와이어가 형성된 것을 확인하였다. 또한 Sn과 MgB2 분말을 함께 적용할 경우 Sn tip을 가진 MgO 나노와이어를 얻을 수 있었다. 이는 Sn이 동시에 촉매의 역할을 하였기 때문일 것으로 추정된다. 한편 Sn과 Bi 혼합분말을 적용한 경우 Bi2Sn2O7 신소재 tip을 포함한 SnO2 나노와이어를 얻을 수 있었다. 이 경우 Bi원자가 적절한 촉매의 역할을 수행한 것으로 사료된다. Substrate의 가열공법에서는 Si wafer상에 각종 금속 즉 Au, Ag, Cu, Co, Mo, W, Pt, Pd등 초박막을 DC sputter 로 형성한후 annealing하는 기술을 사용하였다. 특기할 만한 것은 Co를 사용한 경우 나노와이어의 spring구조를 얻을 수 있었다는 점이다. MOCVD에 의하여는 Ga2O3및 Bi2O3 나노와이어를 비교적 저온에서 합성하였고 In2O3의 경우는 독특한 나노구조를 형성하였고 이의 결정학적 특성에 대하여 조사하였다.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.1 no.2
• /
• pp.79-93
• /
• 1991

With the advent of ULSI, many problems in previous metallization techniques and interconnection materials have become more serious. In this work, selective deposition of copper to fill the submicron contact has been tried. After forming electro-deposited copper films on p-type (100) silicon wafer using 0.75M $CuSO_4{\cdot}$5H_2O$ as an electrolyte, the effect of deposition time, current density and concentration of an additive on film properties were investigated. Film thickness, particle size and resistivity were analyzed by Alpha Step, SEM and 4 - point probe measurement respectively. The deposition rate was about $0.5-0.6\mu\textrm{m}$/min at $2A/dm^2$ and the particle size increased with increasing current density. The resistivities of electro-deposited copper films were about $3-6{\mu}{\Omega}{\cdot}$cm for the particle size above $4000{\AA}$. By the addition of 0.2 g/l gelatin, the particle size was reduced to less than $0.1{\mu}m $ and selective plugging of copper on submicron contacts could be successfully achieved.