• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.93-94
• /
• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.123-124
• /
• 2005

We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.252-255
• /
• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• Transactions on Electrical and Electronic Materials
• /
• v.6 no.5
• /
• pp.225-228
• /
• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.12
• /
• pp.37-42
• /
• 1999

In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography, $SiO_2$ CVD and RIE, Ti/Cu-CVD were carried cut and then, two level Cu interconnects were accomplished. In the results of CMP unit processes, a 4,635 ${\AA}$/min of removal rate, a selectivity of Cu : $SiO_2$ of 150:1, a uniformity of 4.0% are obtained under process conditions of a head pressure of 4 PSI, table and head speed of 25rpm, a oscillation distance of 40 mm, and a slurry flow rate of 40 ml/min. Also 0.18 ${\mu}m\;SiO_2$ via-line patterns are fabricated using 1000 ${\mu}C/cm^2$ dose, 6 minute and 30 second development time and 1 minute and 30 second etching time. And finally sub-0.2 ${\mu}$ twolevel metal interconnects using the developed processes were fabricated and the problems of multilevel interconnects are discussed.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2001.04a
• /
• pp.1117-1120
• /
• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.