• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.440-446
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• 2008

To manufacture the MLCC with X7R for high voltage stability, $BaTiO_3-MgO-MnO_2-Y_2O_3$ with $(Ba_{0.4}Ca_{0.6})SiO_3$ glass frit was formulated. Based on this composition, the addition of $Er_2O_3$ showed that TCC(Temperature Coefficient Capacitance) at $85^{\circ}C$ was improved from 5 % to ${\sim}0\;%$, but the dielectric constant and IR (Insulation Resistance) were decreased. The glass frit improved the dielectric constant and IR, so the appropriate contents of $Er_2O_3$ and glass frit were 0.6 mol% and 1 wt%, respectively. It showed that the dielectric constant and RC constant were 2,550 and 2,000 (${\Omega}F$), respectively in the sintering condition at $1250^{\circ}C$ in PO2 $10^{-7}$ Mpa. The MLCC with $3.2{\times}1.6$ (mm) size and $1\;{\mu}F$ was also suited for X7R with the above composition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.1
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• pp.41-49
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• 2007

RFID in which subminiature IC chip with the indentified information is built a core technique that can recognize, trace and manage various information of an object using radio frequency in the age of Ubiquitous. Several pressing matters about an infringement of Privacy and a security of private information should be settled as soon as possible because an information of specific circumstance can be collected and used without any awareness by others as well as a private information. In addition, various algorithms with high level of security, which is normally used in wire, can be hardly applied to RFID tag because of a lot of restrictions of tag. In this report, designed-RFID tag based on the standard of ISO/IEC 18000-6 and the problems which originated from the technical procedure of that design were analyzed, and the algorithm which could be applied to the designed-tag was also investigated.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.165-171
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• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.3
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• pp.29-34
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• 2021

For the purpose of Application to the small radar sensor, the MMIC Chips, which are the core component of the W-band, was designed in Korea according to the characteristics of the transceiver and manufactured by 60nm GaN and 0.1㎛ GaAs pHEMT process. The output power of PA is 28 dBm at center frequency of W-band and Noise figure is 6.7 dB of switch and LNA MMIC. Output power and Noise figure of MMIC chips developed in domestic was applied to the transmitter and receiver module through W-band waveguide low loss transition structure design and impedance matching to verify the performance after the fabrication are 26.1~27.7 dBm and 7.85~10.57 dB including thermal testing, and which are close to the analysis result. As a result, these are judged that the PA and Switch and LNA MMICs can be applied to the small radar sensor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.2
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• pp.158-163
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• 2023

Recently, the global demands for high voltage power semiconductors are increasing across various industrial fields. The use of electric cars with high safety and convenience is becoming practical, and IGBT modules of 3.3 kV and 1.2 kA or higher are used for electric locomotives. Delicate design and advanced process technology are required, and research on the optimization of high-voltage IGBT parts is urgently needed in the industry. In this study, we attempted to design a simulation process through TCAD (technology computer-aid design) software to optimize the process conditions of the fielding process among the core unit processes for an especial high yield voltage. As well, the prior circuit technology design and a ring pattern with a large number of ring formation structures outside the wafer similar to the chip structure of other companies were constructed for 3.3 kV NPT-IGBT through a unit process demonstration experiment. The ring pattern was designed with 21 rings and the width of the ring was 6.6 ㎛. By changing the spacing between patterns from 17.4 ㎛ to 35.4 ㎛, it was possible to optimize the spacing from 19.2 ㎛ to 18.4 ㎛.

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.867-879
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• 2020

As the era of space technology utilization is approaching, the launch of CAS (Compact Advanced Satellite) 500-1/2 satellites is scheduled during 2021 for acquisition of high-resolution images. Accordingly, the increase of image usability and processing efficiency has been emphasized as key design concepts of the CAS 500-1/2 ground station. In this regard, "CAS 500-1/2 Image Acquisition and Utilization Technology Development" project has been carried out to develop core technologies and processing systems for CAS 500-1/2 data collecting, processing, managing and distributing. In this paper, we introduce the results of the above project. We developed an operation system to generate precision images automatically with GCP (Ground Control Point) chip DB (Database) and DEM (Digital Elevation Model) DB over the entire Korean peninsula. We also developed the system to produce ortho-rectified images indexed to 1:5,000 map grids, and hence set a foundation for ARD (Analysis Ready Data)system. In addition, we linked various application software to the operation system and systematically produce mosaic images, DSM (Digital Surface Model)/DTM (Digital Terrain Model), spatial feature thematic map, and change detection thematic map. The major contribution of the developed system and technologies includes that precision images are to be automatically generated using GCP chip DB for the first time in Korea and the various utilization product technologies incorporated into the operation system of a satellite ground station. The developed operation system has been installed on Korea Land Observation Satellite Information Center of the NGII (National Geographic Information Institute). We expect the system to contribute greatly to the center's work and provide a standard for future ground station systems of earth observation satellites.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.