• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.541-548
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• 2007

The workflow, one of core features for modern business operation, models common elements and their relationships in business processes. The research is focused on how to adapt the workflow model to the healthcare examination which becomes popular these days. Especially, we intend to have fully automated process for healthcare examination by providing customers with PDA with RFTD chip. In order to realize this goal, this paper proposes the design of software architectures the class structures, and the definition of messages used for the system interactions. In other word, the paper shows the analysis of healthcare application in terms of service scenario and the design of workflow engine ant ubiquitous healthcare application under the Object-Oriented programming environment. the The result of the study may also enable the unmanned healthcare examination as well as ubiquitous based healcare examination sooner or later.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.109-109
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• 2017

알지네이트 하이드로 젤은 해조류에서 추출되는 천연 고분자인 알지네이트가 칼슘 또는 마그네슘 양이온과 이온가교(Ioninc cross linking)를 형성할 때 알지네이트의 고분자 구조가 칼슘, 마그네슘 양이온을 감싸면서 형성되는 고분자이다. 알지네이트 하이드로 젤은 높은 생체적합성(Biocompatibility)으로 인해 세포 재생을 위한 조직공학 및 재생의학, 약물전달 등의 제약 관련 분야에 광범위하게 적용될 수 있는 물질로 많은 연구가 이루어지고 있다. 본 연구에서는 마이크로 플루이딕 칩을 이용하여 알지네이트 튜브를 제조하였다. 먼저 유동 포커싱 방식(flow focussing)을 유도할 수 있는 PDMS(Polydimethylsiloxane) 마이크로 플루이딕 칩을 제조하였다. 마이크로 플루이딕 칩은 CNC(Computer Numeric Control) milling machine을 이용한 template를 만들고 NOA mold를 이용하여 최종 PDMS 칩을 제작하였다. 튜브를 만들기 위한 마이크로 채널은 내부 채널 ($200{\times}200um$), 중간 채널 ($200{\times}200um$) 및 외부 채널 ($200{\times}200um$)로 구성되며 내부, 중간, 외부의 유체가 합류하는 수집채널은 폭 500 um, 깊이 200 um로 구성되었다. 운반체로는 5%의 acetic acid를 함유한 mineral oil를 이용하였으며 내부의 core flow는 $H_2O$로 하였다. 중간 유체인 2% 알지네이트 프리폴리머는 칼슘 이온의 존재 하에서 젤화 과정이 매우 빠르기 때문에 마이크로 채널 내부에서의 반응을 제어하고 막힘을 방지하기 위해 수용성 복합 칼슘-에틸렌 디아민 테트라 아세트산 (EDTA)을 사용하였다. 본 마이크로 플루이딕 칩에 각각의 유체를 이동시켰을 때, 운반체인 oil phase의 수소이온은 중간 유체인 알지네이트 프리폴리머와의 계면을 통해 확산되어 Ca-EDTA 복합체로부터 칼슘 양이온의 방출을 유발하게 된다. 방출된 칼슘 양이온은 알지네이트 고분자와의 이온 가교를 통해 알지네이트 하이드로 젤을 형성하여, 각 유체의 flow에 따라 알지네이트 튜브를 쉽고 빠르게 제조 가능하였다. 본 연구에서 제조된 알지네이트 튜브는 인체 내 장기간 약물 전달을 위한 나노섬유로 활용하거나 인공혈관을 구성하는 extracellular matrix로 활용될 잠재력을 가지고 있어 추후 활발한 연구개발이 진행될 예정이다.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.28-36
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• 2008

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.273-280
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• 2017

As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1226-1235
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• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.849-856
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• 2012

Chip on board type white light emitting diode on metal core printed circuit board with high thixotropy silicone is fabricated by vacuum printing encapsulation system. Encapsulant is chosen by taking into account experimental results from differential scanning calorimeter, shearing strength, and optical transmittance. We have observed that radiant flux and package efficacy are increased from 336 mW to 450 mW and from 11.9 lm/W to 36.2 lm/W as single dome diameter is varied from 2.2 mm to 2.8 mm, respectively. Double encapsulation structure with 2.8 mm of dome diameter shows further significant enhancement of radiant flux and package efficacy to 667 mW and 52.4 lm/W, which are 417 mW and 34.8 lm/W at single encapsulation structure, respectively.