• Journal of Powder Materials
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• v.20 no.5
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• pp.355-358
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• 2013

Micro trench structures are applied in gratings, security films, wave guides, and micro fluidics. These micro trench structures have commonly been fabricated by micro electro mechanical system (MEMS) process. However, if the micro trench structures are machined using a diamond tool on large area plate, the resulting process is the most effective manufacturing method for products with high quality surfaces and outstanding optical characteristics. A nonferrous metal has been used as a workpiece; recently, and hybrid materials, including polymer materials, have been applied to mold for display fields. Thus, the machining characteristics of polymer materials should be analyzed. In this study, machining characteristics were compared between nonferrous metals and polymer materials using single crystal diamond (SCD) tools; the use of such materials is increasing in machining applications. The experiment was conducted using a square type diamond tool and a shaper machine tool with cutting depths of 2, 4, 6 and 10 ${\mu}m$ and a cutting speed of 200 mm/s. The machined surfaces, chip, and cutting force were compared through the experiment.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.20-25
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• 2010

An integrated Mach-Zehnder interferometric sensor operating at 632.8 nm was designed and fabricated by the technology of planar rib waveguides. Rib waveguide based on silica system ($SiO_2-SiO_xN_y-SiO_2$) was geometrically designed to have single mode operation and high sensitivity. It was structured by semiconductor fabrication processes such as thin film deposition, photolithography, and RIE (Reactive Ion Etching). With the power observation, propagation loss measurement by cut-back method showed about 4.82 dB/cm for rib waveguides. Additionally the chromium mask process for an etch stop was employed to solve the core damaging problem in patterning the sensing zone on the chip. Refractive index measurement of water/ethanol mixture with this device finally showed a sensitivity of about $\pi$/($4.04{\times}10^{-3}$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.78-86
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• 2010

This paper discusses the programming model of SODA-II that is a baseband processor for software defined radio (SDR) systems. Signal processing On-Demand Architecture Ⅱ (SODA-II) is an on-chip multiprocessor architecture consisting of four processor cores and each core has both an wide SIMD datapath and a scalar datapath. This architecture is appropriate for baseband processing that is a mixture of vector computations and scalar computations. The programming model of the SODA-II is based on C library routines. Because the library routines hide the details of complex SIMD datapath control procedures, end users can easily program the SODA-II without deep understanding on its architecture. In this paper, we discuss the details of library routines and how these routines are exploited in the implementation of baseband signal processing algorithms. As application examples, we show the implementation result of W-CDMA multipath searcher and OFDM demodulator on the SODA-II.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.7
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• pp.791-794
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• 2014

In this work, a 300 GHz imaging detector has been developed and image has been acquired in a 65-nm CMOS technology. The circuit was designed based on the square-law of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 2,270 V/W and minimum NEP of $38pW/Hz^{1/2}$ at 285 GHz, and NEP< ${\sim}200pW/Hz^{1/2}$ for 250~305 GHz range. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.