• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.147-149
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• 2004

Although most of the people have studied English for a long time, their English conversation capability is low. When we provide them portable conversational-type English learners by the application of computer and information process technology, such portable learners can be used to enhance their English conversation capability by their conventional conversation exercises. The core technology to develop such learner is the development of a voice recognition and synthesis module under an embedded environment. This paper deals with voice recognition and synthesis, prototype of the learner module using a DSP(Digital Signal Processing) chip for voice processing, voice playback function, flash memory file system, PC download function using USB ports, English conversation text function by the use of SMC(Smart Media Card) flash memory, LCD display function, MP3 music listening function, etc. Application areas of the prototype equipped with such various functions are vast, i.e. portable language learners, amusement devices, kids toy, control by voice, security by the use of voice, etc.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2283-2288
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• 2006

As development in technology of bioinformatics recently makes it possible to operate micro-level experiments, we can observe the expression pattern of total genome through on chip and analyze the interactions of thousands of genes at the same time. Thus, DNA microarray technology presents the new directions of understandings for complex organisms. Therefore, it is required how to analyze the enormous gene information obtained through this technology effectively. In this thesis, We used sample data of bioinformatics core group in harvard university. It designed and implemented system that evaluate accuracy after dividing in class of two using Bayesian algorithm, ASA, of feature extraction method through normalization process, reducing or removing of noise that occupy by various factor in microarray experiment. It was represented accuracy of 98.23% after Lowess normalization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.

• The Journal of the Korea Contents Association
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• v.8 no.5
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• pp.104-112
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• 2008

RFID/USN is considered important basic infra of ubiquitous community and tried practical adaption through various research. Specially, there is during researcher progresses for stock and state management of logistics to let you get at u-mart systems. It discern thing from warehouse to deliver as adhere RFID tag of palette in keeping unit of article and construct form of thing to analyze information of environment status using sence module based on function of wireless communication. in the paper, propose composition of customer satisfaction system using RFID chip in u-Mart status management system based on RFID/USN and according to analysis specific information of commodity, propose movement reader device to offer real-time information from customer. And it presents the improvement program for the provision of product information which is appropriate uses the RFID chip and the provision of control information in the customer who is a core of consuming.