• 전력전자학회논문지
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• 제22권1호
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• pp.9-17
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• 2017

A parallel control algorithm of thyristor dual-converter power system for the DC power supply of railway is proposed. The circulating current and current imbalance generated during parallel operation can be limited to control the output voltage of each power system by using the proposed parallel control algorithm. The proposed control algorithm can also eliminate output current sensor to achieve the same output response without additional costs. The validity of the proposed algorithm is verified through simulation and experiment.

• 소음진동
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• 제6권5호
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• pp.671-677
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• 1996

This paper presents the analytical method for predicting turbulence- induced noise in the multilayered cylinder composed of an outer hose, an inner fluid and an internal core. It is assumed that an infinite axisymmetric cylinder is located horizontally in water with free stream velocity and the turbulent boundary layer (TBL) surrounding the outer hose is fully developed and homogeneous. The transfer function at the core surface due to the propagation of the pressure fluctuation within the TBL is formulated using the linearized Navier-Stockes equation for solid and fluid. In the estimation of the energy spectrum of wall pressure fluctuation, the empirical formula proposed by Strawderman based on the Corcos model is used. A general algorithm for the calculation of the pressure level at the surface of a core, that is, turbulence- induced noise, is presented. Through the detailed numerical simulation, it is found that the major noise mechanism is the propagation of the bulge wave along hose.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.85-87
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• 2012

This paper describes the design and analysis of an integrated transformer magnetic core which comprises of two different power cores with PFC inductor and LLC resonant transformer magnetic cores. The equivalent magnetic circuit modeling approach is employed to analyze the variations in coupling coefficient and inductance in terms of air gaps under the operations of the respective power core. Simulation and experimental studies are performed with a fabricated prototype integrated core and their results are discussed.

• 한국컴퓨터정보학회논문지
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• 제7권4호
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• pp.89-93
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• 2002

본 논문에서는 32비트 DSP에 사용 가능한 ALU를 설계하였다. 이 ALU는 32비트 연산을 기본 단위로 하고 있으며 5단 파이프라인 중에서 execution 단계에 해당된다. ALU에서 지원하는 기능은 덧셈, 뺄셈, 나눗셈과 같은 산술연산, AND, XOR과 같은 논리연산, 그리고 쉬프트 등이다. 기능별로 여러 기능 블록을 사용하지 않는 대신 몇 개의 기능 블록만을 만들고, 회로 동작이 이 기능 블록들을 공유하도록 설계하였으며, ALU를 설계하기 위해 각 기능 블록을 HDL로 기술하여 시뮬레이션을 수행하였다. 이ALU는 32 비트 DSP에 사용 가능하도록 설계되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2000년도 KIASC Conference 2000 / 2000년도 학술대회 논문집
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• pp.154-157
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• 2000

Superconducting tape easily can applied to distribution of electricity. It designs basic model of Saturable Reactor type Fault Current Limiter which used superconducting tape, and observes a specific character by means of simulation. Saturable Reactor type Fault Current Limiter is not influenced by saturation of Magnet core appeared in Induction Fault Current Limiter, because it exploit saturation of Iron core. But, it is possible that superconducting tape quenched when AC current flow to superconducting tape which biased DC voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.21-23
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• 1995

The analysis of the thin lamination model of the wound core type transformer by FEM requires many region division and much calculationg time, and it has difficulty in calculation by modem computer. A new method which is simulated by a solid but anisotropic block with the magnetic permeabilities in the orthogonal dimension, is selected to account for the presence of the lamination.[1] Based on this equivalent anisotropic block model, we analyze the iron loss of the wound core type transformer by FEM, and compare the simulation results with the experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.918-919
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• 2008

This paper deals with the DC-DC converter with high efficiency using the minimum reactor. In this paper, the proposed convert uses the air core reactor for ZCS(zero currunt switching) which can minimize the core losses and removes the over switching losses by soft switching. The proposed converter is verified by the modes analysis and computer simulation to prove the theoretical background and adequacy.

• 한국방사성폐기물학회:학술대회논문집
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• 한국방사성폐기물학회 2005년도 춘계 학술대회
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• pp.255-263
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• 2005

Migration experiments of THO and 237Np have performed through a sampled granite core in Chemlab2 probe at the Aspo hard Rock laboratory. The elution curves of THO were analysed to determine hydraulic properties such as the extent of dispersion effect according to flow rates. The retardation phenomena of the solutes were observed and described with elution curves and migration plumes. After migration test, the rock core was opened, and the remaining radioactivities on the rock fracture surfaces were measured. The transport process was simulated with a two-dimensional channel model. The mass transport process was described with three types of basic processes ; advection, sorption and matrix diffusion. By the combination of these processes, effects of each process on transport were described in terms of elution curves and migration plumes. By comparing the simulation results to the experimental one, it was possible to analyse the retardation effect quantitatively.