• Title/Summary/Keyword: Core design

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A Study on Stability of Single-layer Space Frame Structure for Energy Core of Incheon Airport Second Terminal (인천공항 제2터미널 에너지코어 단층 스페이스 프레임 구조물의 안정에 관한 연구)

  • Jung, Hwan-Mok
    • Journal of Korean Association for Spatial Structures
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    • v.15 no.4
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    • pp.49-56
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    • 2015
  • The roof grid of single-layer space frame structure, for Energy Core of Incheon Airport Second Terminal, is very simple and aesthetic, but it is apt to buckle under external force because of mild curvature and complex shape. The object of this study is to estimate the stability of single-layer space frame structures for Energy Core of Incheon Airport Second Terminal with the analytical conditions of structural design. The results show that the buckling load of model(pin-pin, uniform load, rigid joint), that is, the most similar model to the analytical conditions of structural design. was $10.7kN/m^2$.

The Use of System for Design Verification of PCI Express Endpoint RTL Core

  • Kim Sun-Wook;Kim Young-Woo;Park Kyoung
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.285-288
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    • 2004
  • In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

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Design Space Exploration of Many-Core Architecture for Sound Synthesis of Guitar on Portable Device (휴대 장치용 기타 음 합성을 위한 매니코어 아키텍처의 디자인 공간 탐색)

  • Kang, Myeongsu;Kim, Jong-Myon
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2014.01a
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    • pp.1-4
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    • 2014
  • Although physical modeling synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research of single-instruction multiple-data many-core architectures that support the tremendous amount of computations by exploiting massive parallelism inherent in physical modeling synthesis. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, design space exploration is conducted for seven processing element (PE) configurations. To find an optimal PE configuration, each PE configuration is evaluated in terms of execution time, area and energy efficiencies. Experimental results show that all PE configurations are satisfied with the system requirements to be implemented in portable devices.

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A Design of AES-based Key Wrap/Unwrap Core for WiBro Security (와이브로 보안용 AES기반의 Key Wrap/Unwrap 코어 설계)

  • Kim, Jong-Hwan;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.7
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    • pp.1332-1340
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    • 2007
  • This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

PWR core calculation based on pin-cell homogenization in three-dimensional pin-by-pin geometry

  • Bin Zhang;Yunzhao Li;Hongchun Wu;Wenbo Zhao;Chao Fang;Zhaohu Gong;Qing Li;Xiaoming Chai;Junchong Yu
    • Nuclear Engineering and Technology
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    • v.56 no.6
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    • pp.1950-1958
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    • 2024
  • For the pressurized water reactor two-step calculation, the traditional assembly homogenization and two-group neutron diffusion calculation have been widely used. When it comes to the core pin-by-pin simulation, many models and techniques are different and unsettled. In this paper, the homogenization methods based on the pin discontinuity factors and super homogenization factors are used to get the pin-cell homogenized parameters. The heterogeneous leakage model is applied to modify the infinite flux spectrum of the single assembly with reflective boundary condition and to determine the diffusion coefficients for the SP3 solver which is used in the core simulation. To reduce the environment effect of the single-assembly reflective boundary condition, the online method for the SPH factors updating is applied in this paper, and the functionalization of SPH factors based on the least-squares method will be pre-made alone with the table of the group constants. The fitting function will be used to update the thermal-group SPH factors with a whole-core pin-by-pin homogeneous solution online. The three-dimensional Watts Bar Nuclear Unit 1 (WBN1) problem was utilized to test the performance of pin-by-pin calculation. And numerical results have demonstrated that PWR pin-by-pin core calculation has more accurate results compared with the traditional assembly-homogenization scheme.

A Study on an Analysis of Core Information Literacy Competencies for Information Literacy Instruction of Undergraduate Students in Design Discipline (디자인분야 대학생의 정보문해 교육을 위한 핵심 정보문해능력 분석에 관한 연구)

  • Kim, Sun-Hi
    • Journal of the Korean Society for information Management
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    • v.23 no.1 s.59
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    • pp.5-39
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    • 2006
  • Design discipline requires more specialized and sophisticated information literacy competencies necessary to effectively find and apply the information that students need for their teaming and the future independent designer than are outlined in general information literacy competencies. Therefore, The goals of this study is to identify specific information literacy competencies within the Design Discipline. This research analyzed design-specific core information literacy competencies through the literature analysis on the design goals & curriculum of four domestic universities and the NASAD standards & guidelines and verified those by Delphi Survey. The result showed that design discipline requires commonly 26 specific core competencies in seven broad categories and the these competencies are related to the time for information literacy Instruction. Also, The result analyzed that such majors in design as product design, visual design, need additionally more specialized and detailed competencies with specific focus and that design discipline requires commonly the information literacy competencies about general studies & fundamental ability.

A Methodological Shift in Building Design through Development of Collaborative Design Platforms

  • Schumacher, Jonatan;Naugle, Matthew
    • International Journal of High-Rise Buildings
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    • v.3 no.4
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    • pp.279-283
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    • 2014
  • This paper introduces two platforms created by the development team at CORE studio, Thornton Tomasetti's global innovation studio. Collaborative platforms change the way that parties communicate and develop projects. Wikipedia is one of many great examples for a platform that supports collaborative development of a product - the world's largest encyclopedia. In the AEC industry, no such platform exists that can be used for collaborative development of a building project, and hence, information exchange between the parties involved, and modeling programs used in a project is slow and opaque. The platforms introduced in this paper allow for much greater transparency at all stages of the building design process, and hence improve the flow of information between parties involved in the process, both firm-internal and external. While traditionally, the use of a large number of different modeling and analysis platforms is hard to manage by a project team; this paper introduces methods that strengthen the design process by using a multitude of programs needed in the different building design phases.

Nuclear Core Design for a Marine Small Power Reactor (선박용 소형동력로의 노심 핵설계)

  • 최유선;김종채;김명현
    • Journal of Energy Engineering
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    • v.5 no.2
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    • pp.146-152
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    • 1996
  • A small power reactor core of 108 MW$\_$th/ was designed with some design constraints: 2 year refueling cycle length, soluble boron free operation, low power density, and proven fuel assembly design - Uljin 3'||'&'||'4 design specifications. CASMO-3 and KINS-3 was used to evaluate operational capability for power level control via control rods. Cycle length, power peaking factor, M.T.C., and power coefficients were also checked. Designed core loaded with KOFAs satisfied all design goals. We found that much more burnable poisons are to be loaded with axial enrichment zoning. Control rod assemblies should be located at every other assemblies with more than 3 banks. Additional shutdown banks are proposed for the safe plant cooldown, which could be located at core periphery.

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Design of a dedicated DSP core for speech coder using dual MACs (Dual MAC를 이용한 음성 부호화기용 DSP Core 설계에 관한 연구)

  • 박주현
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1995.06a
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    • pp.137-140
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    • 1995
  • In the paper, CDMA's vocoder algorithm, QCELP, was analyzed. And, 16-bit programmable DSP core for QCELP was designed. When it is used two MACs in DSP, we can implement low-power DSP and estimate decrease of parameter computation speed. Also, we implemented in FIFO memory using register file to increase the access time of the data. This DSP was designed using logic synthesis tool, COMPASS, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

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The study of bending and buckling behavior of sandwich structure according to design parameter variation (설계변수 변화에 따른 샌드위치 구조물의 굽힘 및 좌굴 거동에 관한 연구)

  • 한근조;안성찬;안성찬;김진영
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.10a
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    • pp.841-844
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    • 1997
  • Sandwich structure is widely used in various fields of industry due to its excellent strength and stiffness compared with weight. We studied the buckling and bending behavior with respect to the variation of design parameters such as length, height, and thickness of honeycomb sandwich core. We found that as the density and the thickness of core become higher, the value of critical bucking load increased significantly. We found that the effect of bending stress due to critical buckling load resulted in high bending stress and the value of bending stress decreased in half according to the increase of length of core. The effect by bending stress is dominant above the portion of the intersection line between bending stress and the effect of buckling is dominant below the potion of it. We could get proper thickness ratio and density of core according to applied load conditions.

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