• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.8
• /
• pp.2120-2130
• /
• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.1123-1126
• /
• 1999

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.

• Proceedings of the KIEE Conference
• /
• 2008.10c
• /
• pp.246-247
• /
• 2008

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.11
• /
• pp.2017-2022
• /
• 2007

In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2008.11a
• /
• pp.251-253
• /
• 2008

최근 유럽에서 DVB-T HDTV 방송 표준이 정하지면서 오디오 포맷으로 HE-AAC가 채택되었다. HE-AAC는 압축효율은 높지만 연산량이 높아 낮은 성능의 DSP에서 수행하기에는 어려움이 있다. DVB-T에서는 5.1채널을 사용하고 있어 더욱더 많은 연산을 필요로 한다. 본 논문은 ISO/DEC 14496-3 MPEG4 HE(High Efficiency)-AAC의 Level4에 해당하는 Multichannel Decoder를 최적화하여 구현하고. 가장 많은 연산을 필요로 하는 Synthesis Filter Bank에 제안된 알고리즘을 적용하여 연산량을 줄였고 대부분의 연산부를 어셈블리로 코드 최적화를 하여 작은 성능의 DSP를 사용하여 실시간 Multichannel HE-AAC Audio Decoder의 구현이 가능하게 하였다. DVB-T 오디오 시스템에 필수로 필요한 Audio Description, Dynamic Range Control, Downmix 등을 함께 구현하여 실제 수신기에 사용이 가능하도록 하였다. DSP는 Samsung의 CalmRISC16 + MAC24 core 를 사용하였다.

• Proceedings of the Korea Inteligent Information System Society Conference
• /
• 2006.06a
• /
• pp.311-315
• /
• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.62-68
• /
• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.17 no.4
• /
• pp.477-482
• /
• 2007

This paper presents an audio decoder architecture which can decode AC-3 and MPEG-2 audio bit-streams efficiently. MPEG-2 synthesis filtering is modified by the 32-point FFT to share the common data path with the AC-3's. A programmable Audio DSP core and a hardwired common synthesis tilter are incorporated for effective decoding of two different formats.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.43-53
• /
• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.3
• /
• pp.119-124
• /
• 2009

In this paper, AMR-WB+ audio coder is implemented, in real-time, using Intel 400MHz Xscale PXA250 with 32bit RISC processor ARM9E-J(R)core. The assembly code for ARM9E-J(R)core is developed through the serial process of C code optimization, cross compile, assembly code manual optimization and adjusting the optimized code to Embedded Visual C++ platform. C code is trimmed on Visual C++ platform. Cross compile and assembly code manual optimization are performed on CodeWarrior with ARM compiler. Through these stages the code for both ARM EVM board and PDA is implemented. The average complexities of the code are 160.75MHz on encoder and 33.05MHz on decoder. In case of static link library(SLL), the required memories are 65.21Kbyte, 32.01Kbyte and 279.81Kbyte on encoder, decoder and common sources, respectively. The implemented coder is evaluated using 16 test vectors given by 3GPP to verify the bit-exactness of the coder.