• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.55-58
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• 2001

In this paper, we present the development of a JavaCard for public key crypto algorithms and its performance evaluation. To make a high performance for the public key crypto algorithm such as RSA and ECC on a JavaCard, we have implemented a crypto coprocessor in hardware and ported it to the card operating system and virtual machine environments. The performance of the public key crypto algorithms on the JavaCard shows that our JavaCard is suitable for If card applications which needs high performance and high level of security.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.869-873
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• 1992

A fuzzy controller is designed for compensating the cross-coupling effect of induced roll due to the dynamic characteristics of three fin torpedo. Since the utilization of fuzzy-coprocessor has many interfacing problems with typical microprocessors of the guidance and control unit, the simplified fuzzy inference method based on nonfuzzy-processor is proposed to implement fuzzy controllers of three fin torpedo. This method provides a flexible rule-base design to guarantee the robust control. The good potential of the proposed design is shown through real-time simulations using both a mathematical model on AD-100 computer and an implemented controller on Intel 80C186/80C 187 microprocessors employing 12bit A/D converter.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.1-10
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• 1998

The first thing in designing application-specific instruction set processor is having instruction set closely matching hardware characteristics. This instruction set design problem can be more complicated when cobined with implementation method selection problem of each instruction. Our processor model supports two kinds of instructions-primitive or special instructions. Primitive instructions are implemented using common multifunctional hardware such as ALU. Special instructions require a set of dedicated hardware, which actually functions as a coprocessor to the main processor. In this case, special instructions and primitive instructions can be executed independently. In this paper, we present novel algorithm for genrating special instructions for given application. Parallelism between special instructions and primitive instructions is also considered during the performance estimation stage of generated special instructions.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1551-1554
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• 2002

In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.533-536
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• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.809-810
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• 2006

An H.264 algorithm is commonly used for video compression applications. This algorithm requires a large number of data computations, for example, the sum of absolute difference (SAD) operation. We analyzed H.264 reference encoding workloads. The H.264 encoding program has 8.78% SAD operation. The SAD operation is to sum up 16 difference-values in H.264 $4{\times}4$ sub-blocks. In order to accelerate SAD operations, we implemented an application specific instruction-set processor (ASIP) that can execute SAD and data transfer instructions. The proposed coprocessor has an absolute value generator and a carry save adder (CSA) unit to sum up 8 difference-values per one clock cycle. We completed SAD operation in 2 clock cycles. Experimental results show that the performance is improved by 34% of total execution time.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1390-1393
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• 1993

An 8b Fuzzy Coprocessor (FC) is presented that has eight programmable fuzzy algorithms and up to 256 inputs, 64 outputs and 16,384 rules. The 6.4mm2 chip fabricated in 1.0$\mu\textrm{m}$ CMOS technology can be used as a stand-alone device or as a macrocell for microcontrollers. Operating at 20MHz crystal frequency, it has a peak performance of 7.9M rules/s. Perspectives of future FC generations are also outlined, including a 12-16b resolution, additional fuzzy set operations, and optimized inference and defuzzification strategies.