• Journal of the Korean institute of surface engineering
• /
• v.4 no.1
• /
• pp.16-23
• /
• 1971

In this study , fluoborte solution consisting of lead fluoborate, tin fluoborate and cupric acetate was used. By addition of small amount of Cu+= ion to the solution, the Cu content of deposition layer was almost controlled less than 5%. The amount of Cu in deposition layer was almost constant without any influence of Pb++ & Sn++ in the solution, and the amount of Pb was increased by the increase of total concentration of Pb++ +Sn++ in the solution, and the amount of Pb was increased by the increase of total concentration of Pb++ +Sn++ in the solution . Agitation of plating solution & low current density result in the increase of Cu content. Analyzing of microscopic structures and etching tests of the deposited alloy, it was believed that the alloy had a lamellar structure consisting of copper rich lamellar and lead rich layer.

• Proceedings of the KSME Conference
• /
• 2004.04a
• /
• pp.1364-1369
• /
• 2004

New method for the design, fabrication, and calibration of micro-machined heat flux sensor has been developed. Two types of micro-machined heat flux sensor having different thicknesses of the thermal-resistance layer are fabricated using the MEMS technique. Photo-resist patterning using a chrome mask, bulk-etching and copper-nickel sputtering using a shadow mask are applied to make heat flux sensors, which are calibrated in the convection-type heat flux calibration facility. The sensitivity of the device varies with thermal-resistance layer, and hence can be used to measure the heat flux in heat-transfer phenomena.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.494-497
• /
• 2003

We report the dark spots in organic light emitting diodes by using a near-field scanning microwave microscope. Devices structure was glass / indium-tin-oxide(ITO) / copper-pthalocyiane(Cu-Pc) / tris-(8-hydroquinoline)aluminum(Alq3) / aluminum(Al). We made artificial dark spots by using a etching technique on a ITO substrate. Near-field scanning microwave microscope images and reflective coefficient of dark spots were measured and compared by the change of various applied voltage changes 0-15V.

• Bulletin of the Korean Chemical Society
• /
• v.10 no.1
• /
• pp.30-32
• /
• 1989

Traces of nine elements, gold, arsenic, cobalt, chromium, copper, europium, hafnium, sodium and antimony in commercially available silicon crystals were determined by the instrumental neutron activation analysis using the single comparator method. The values of the concentrations of these elements in both single and polycrystals were found to decrease significantly to a low limiting level by simply washing and etching surface contaminants having been introduced during various steps of sample preparation and irradiation. However, the chromium levels in polycrystals were not easily decreased, these depending upon the cutting tools employed. The Sb-doped content in each semiconductor has been compared with the associated quantities such as the concentration and the conductivity range given by the sample donor. Uncertainty in the sodium analysis due to the fission neutron reaction by silicon itself was discussed.

• Journal of the Korean Society for Precision Engineering
• /
• v.25 no.11
• /
• pp.90-94
• /
• 2008

Recently, a great deal of research is focused on the printed electronics. One of their mainly concerned products is printed RFID tag. RFID technology has attracted researchers and enterprises as a promising method for automatic identification, and they are expected to replace conventional bar codes in inventory tracking and management. The key to successful RFID technology lies in developing low-cost RFID tags and the first step in applying printing technology to RFID systems is to replace antennas that are conventionally produced by etching copper or aluminum. However, due to the printing quality variations, errors, and lower conductivity, the performance of the printed RFID antennas is lower than that of antennas manufactured by conventional etching methods. In this paper, the effect of variations in the printing conditions on the antenna performance is investigated. Three levels for each condition parameter is assumed and effect on the resonant frequency are examined experimentally based on orthogonal array. The most serious factor that affects the resonant frequency of the antenna is the non-uniformity of the edge and the resonant frequency is found to be lower as the non-uniformity increases.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2018.06a
• /
• pp.140-140
• /
• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.565-566
• /
• 2006

Slurry used in metal chemical mechanical polishing normally consists of an oxidizer, a complexing agent, a corrosion inhibitor and an abrasive. This paper investigates effects of citric acid as a complexing agent for Cu CMP with $H_2O_2$ as an oxidizer. In order to study chemical effects of a citric acid, x-ray photoelectron spectroscopy were performed on Cu sample after Cu etching test. XPS results reveal that CuO, $Cu(OH)_2$ layer decrease but Cu/$Cu_2O$ layer increase on Cu sample surface. To investigate nanomechanical properties of Cu sample surface, nanoindentation was performed on Cu sample. Results of nanoindentation indicate wear resistance of Cu Surface decrease. According to decrease of wear resistance on Cu surface, removal rate increases from $285\;{\AA}/min$ to $8645\;{\AA}/min$ in Cu CMP.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.3
• /
• pp.79-84
• /
• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Korean institute of surface engineering
• /
• v.42 no.5
• /
• pp.216-219
• /
• 2009

A surface acoustic wave (SAW) filter structure was fabricated employing $4{\mu}m$ thick nanocrystalline diamond (NCD) and $2.2{\mu}m$ thick ZnO films on Si wafer. The NCD film was deposited in an $Ar/CH_4$ gas mixture by microwave plasma chemical vapor deposition method. The ZnO film was formed over the NCD film in an RF magnetron sputter using ZnO target and $Ar/O_2$ gas. On the top of the two layers, copper film was deposited by the RF sputter and inter digital transducer (IDT) electrode pattern (line/space : $1.5/1.5{\mu}m$) was defined by the photolithography including a lift-off etching process. The fabricated SAW filter exhibited the center frequency of 1.66 GHz and the phase velocity of 9,960 m/s, which demonstrated that a giga Hertz SAW filter can be realized by utilizing the nanocrystalline diamond thin film.