• Journal of the Institute of Convergence Signal Processing
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• v.6 no.1
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• pp.39-44
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• 2005

Scheduling for digital system synthesis is assigning each operation in a control/data flow graph(CDFG) to a specific control step without violating precedence relation. It is one of the most important tasks due to its direct influence on the performance of the hardware synthesized. In this paper, we propose a resource-constrained scheduling algorithm. Our algorithm first analyzes the given CDFG to determine the number of functional units of each type, then assigns each operation to a control step while satisfying the constraints. It also tries to improve the solution iteratively by adjusting the number of functional units using the results collected from the previous scheduling. Experiments were performed to test the performance of the proposed algorithm, and results are presented

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.773-777
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• 2005

This article is about using information technology to apply with water loss inspection system in District Metering Area (DMA). Inspector can check Flow rate and Minimum Night Flow; NMF via Smart Phone or PDA include sending SMS Alert in case the Pressure, Flow rate and NMF is over the range of controlling. This will be used as equipment to implement water loss in international proactive and can keep on water loss reduction more efficiency. The system consists of Data Logger which collects data of Flow rate from DMA Master Meter. PC is Wap Server which dial via modem in order to get data through FTP Protocal that will convert text file to Microsoft Access Database. Wappage will use xhtml language to show database on Wapbrowser and can show the result on Smart Phone or PDA by graph and table for system analysis.

• The KIPS Transactions:PartD
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• v.13D no.1 s.104
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• pp.117-124
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• 2006

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• Journal of the Korea Society of Computer and Information
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• v.1 no.1
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• pp.147-158
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• 1996

This paper proposed a concurrency control structure based on specialized data flow graphs that was analysed a run-time concurrency control activity to be integrated with the task scheduler Data were viewed as flowing on the arcs from one node to another in a stream of discrete to tokens. The network that Is based upon the Entity-Relationship model, can be viewed a fixed problems used query tokens as a data flow graph. The performance was measured used in the various expriments compared the overall performance of the different concurrency control methods, DBFG (DataBase Flow graphs) scheduling had the knowledge to obtain better performance than 2PL in a distributed environment.

• Journal of KIISE:Software and Applications
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• v.28 no.12
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• pp.910-920
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• 2001

We developed a SIFC(Slice-based Information Flow Graph) For modeling the information flow on program on the basis of the information flow of a data tokens on program slices. Then we defined a SCM(Slice-based Complexity Measure) for measuring the program complexity by measuring the complexity of information flow on SIFG, We showed that, according to Zuse's approach, it assumed ordinal scale based on atomic modifications on SIFG and that it was additive to binary operation MBSEQ and that it was not additive to binary operation MBALT but satisfied Weyuker's 9th axiom. Also based on comparison with the existing measures, we showed that SCM could measure not only the control and data flow in program but also the physical size of program.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.44-48
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• 1998

In this paper proposed Component Synthesis Algorithm(CSA) for mapping described HDL to RT component of given library. CSA transform I/O variables of HDL and relation of operators to control/data flow graph(CDFG) that consists of graph, reduce the size of graph, compute the cost, the bound, and the method that use compatibility graph(CG), and then mapping to component. Component synthesis used branch-and-bound algorithm. The result that synthesis using CSA algorithm was proved that this result and the cost of the manual were indentified.

• ETRI Journal
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• v.39 no.3
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• pp.345-352
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• 2017

Traffic management is a highly beneficial mechanism for satisfying quality-of-service requirements and overcoming the resource scarcity problems in networks. This paper introduces an optimal connection admission control mechanism to decrease the packet loss ratio and end-to-end delay in cognitive radio sensor networks (CRSNs). This mechanism admits data flows based on the value of information sent by the sensor nodes, the network state, and the estimated required resources of the data flows. The number of required channels of each data flow is estimated using a proposed formula that is inspired by a graph coloring approach. The proposed admission control mechanism is formulated as a semi-Markov decision process and a linear programming problem is derived to obtain the optimal admission control policy for obtaining the maximum reward. Simulation results demonstrate that the proposed mechanism outperforms a recently proposed admission control mechanism in CRSNs.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.410-413
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• 2000

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.212-215
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• 2002

In this paper, we present an intermediate representation CDFG(Control Data Flow Graph) and an efficient scheduling technique for low power circuit design. The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, iterative rescheduling process are performed in a minimum bound estimation, starting with the as soon as possible as scheduling result, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.104-114
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• 1995

In this paper, an intermediate representation HSFG(Hanyang Sequential Flow GRaph) and a new scheduling algorithm for the control-dominated ASIC design is presented. The HSFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. The scheduling algorithm minimizes the total operating time by reducing the number of the constraints as maximal as possible, searching a few paths among all the paths produced by conditional branches. The constraints are substitute by subgraphs, and then the number of subgraphs (that is the number kof the constraints) is minimized by using the inclusion and overlap relation among subgraphs. The proposed algorithm has achieved the better results than the previous ones on the benchmark data.