• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.619-630
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• 2003

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.292-294
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• 2003

최근들어 IT 산업이 급속도로 발전하면서, 리소스가 제한된 작은 기기들의 사용이 비약적으로 증가하는 추세에 있다. 이들 기기들에 플랫폼 독립성(Platform Independency), 보안성(Security), 이동성(Mobility) 등의 장점을 포함하고 있는 자바 환경을 적용하기 위해 연구가 계속되고 있다. 임베디드 시스템이나 모바일 시스템과 같이 자원이 제한적인 다양한 기기들에는 자바 가상 머신을 경량화한 최소 크기의 자바 플랫폼에 대한 Configuration인 CLDC(Connected, Limited Device Configuration)에서 정의하고 있는 K 가상 머신(K Virtual Machine: KVM)을 탑재한다. 본 논문에서는 실시간 운영체제로 iRTOS$^{TM}$을 사용하는 기기에서 KVM을 탑재할 때 필요한 메모리 체계를 설계하고 구현한 내용을 설명한다.

• Journal of the Speleological Society of Korea
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• no.80
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• pp.11-19
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• 2007

Most studies in the past in testing and benchmarking on Intrusion Detection System (IDS) were conducted as comparisons, rather than evaluation, on different IDSs. This paper presents the evaluation of the performance of one of the open source IDS, snort, in an inexpensive high availability system configuration. Redundancy and fault tolerance technology are used in deploying such IDS, because of the possible attacks that can make snort exhaust resources, degrade in performance and even crash. Several test data are used in such environment and yielded different results. CPU speed, Disk usage, memory utilization and other resources of the IDS host are also monitored. Test results with the proposed system configuration environment shows much better system availability and reliability, especially on security systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.505-518
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• 1987

In this paper, the 2-level and 3-level types of PWM technique have been analyzed, and a multiprocessor has been designed as controller for these two types of PWM inverters. Designed multiprocessor employing a hierarchical structure of a SUPERVISORY PROCESSOR which interconnects three LOCAL PROCESSOR through a common memory technique has showed as elaborate digital control characteristic. Using this multiprocessor configuration the system could gain a great degree of freedom in change of software. Also software was simpler than a single processor configuration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.88-92
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• 2004

Most studies in the past in testing and benchmarking on Intrusion Detection System (IDS) were conducted as comparisons, rather than evaluation, on different IDSs. This paper presents the evaluation of the performance of one of the open source IDS, snort, in an inexpensive high availability system configuration. Redundancy and fault tolerance technology are used in deploying such IDS, because of the possible attacks that can make snort exhaust resources, degrade in performance and even crash. Several test data are used in such environment and yielded different results. CPU speed, Disk usage, memory utilization and other resources of the IDS host are also monitored. Test results with the proposed system configuration environment show much better system availability and reliability, especially on security systems.

• International journal of advanced smart convergence
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• v.11 no.1
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.653-655
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• 2013

This paper is the study of Multiple External Storage Configuration for the Android based Set-top Box system. Because of Mobile OS, Android has limitation in media streaming, recording and playing for Set-top box function with only support external storage device Micro-SD card. In this paper, we research for the Multiple External Storage configuration for external disk drive, USB Memory, SD card. in Android System with Multi-Volume Management system implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.3
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• pp.11-17
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• 1978

A medium scale integrated circuit, BCD to seven segment decoder/driver is designed and fabricated by employing P-channel metal-oxide-semiconductor technology. The device configuration is specifically designed for a common cathode seven segment LED display unit. The decoder logic is composed of two serially connected read-only-memory matrices and the LED drivers are implemented with wide channel FET's. The fabricated integrated circuit performed successfully with a supply voltage between -7 Volt and -26 Volt and the non-uniformity of the LED segment current is about 10%.