• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.18-29
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• 2008

NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.459-466
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• 2007

TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.308-314
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• 2010

As the price of flash memory continues to drop and the technology of flash SSD controller innovates, high performance flash SSDs with affordable prices flourish in the storage market. Nevertheless, it is hard to expect that flash SSDs will replace harddisks completely as database storage. Instead, the approach to use flash SSD as a cache for harddisks would be more practical, and, in fact, several hybrid storage architectures for flash memory and harddisk have been suggested in the literature. In this paper, we propose a new approach to use flash SSD as an extended buffer for main buffer in database systems, which stores the pages replaced out from main buffer and returns the pages which are re-referenced in the upper buffer layer, improving the system performance drastically. In contrast to the existing approaches to use flash SSD as a cache in the lower storage layer, our approach, which uses flash SSD as an extended buffer in the upper host, can provide fast random read speed for the warm pages which are being replaced out from the limited main buffer. In fact, for all the pages which are missing from the main buffer in a real TPC-C trace, the hit ratio in the extended buffer could be more than 60%, and this supports our conjecture that our simple extended buffer approach could be very effective as a cache. In terms of performance/price, our extended buffer architecture outperforms two other alternative approaches with the same cost, 1) large main buffer and 2) more harddisks.

• Architectural research
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• v.8 no.1
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• pp.1-7
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• 2006

Various housing measures are needed for the rapidly aging society of Korea. In particular, the welfare policy for the elderly has changed towards the community care. Taking this fact into consideration, it is necessary to have the establishment of a system that offers the elderly appropriate welfare services at their appropriate residence (ageing in place) for the effectiveness of the community care. In this aspect, there are a number of implications to Korea to study merits and demerits of the Health Facilities for the Aged (HFA) in Japan. The society of Japan has been rapidly aging since 1970, and Korea is to face the same situation. As for the data of this study, a total of 2,393 facilities (as of November 1999) mentioned in the annual report of the Japanese Ministry of Health, Labor and Welfare were classified based on types of their establishment: (1) free-standing structures (603 facilities); (2) annexes to hospitals (981 facilities); (3) annexes to welfare facilities (511 facilities); and (4) annexes to clinics (298 facilities). Next, 239 facilities were selected through taking a sample of 10 percent from each type of the HFA mentioned above. This was done through the random sampling method with the computer program of MS EXCEL. The Implications of the results of analyses are as follows. First, most of the health facilities were planned with the scale that was larger than the scale of standard special nursing homes in terms of the total floor area. Precise equations that were to obtain precise results of the scale of the HFA and the appropriate number of residents were obtained through the method of the regression analysis. Korea and Japan have similarities in terms of culture, society and family relations; however, the two countries also have differences in terms of the application of laws on the establishment of houses, hospitals, and welfare facilities. As for planning the scale of the HFA, the realities of Korea should be considered. Second, as for the functional aspect of the HFA with a condition of returning home, the place before and after the HFA showed the pattern of 'from a residential place to a residential place' and 'from a hospital to a hospital.' This reveals a close correlation with the types of the HFAs and operational ways of the facilities. Its cause is considered to be the aspect of the operation and management of the HFA rather than the aspect of its function of providing services in association with medical and health facilities. Therefore, when intermediate welfare facilities are considered in Korea, it is strongly advised to consider the problem of annexes to other facilities and efficiency of sharing of the facilities in terms of its operation and management.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.239-251
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• 2010

In modern distributed enterprise applications that have multilayered architecture, business entities are a kind of crosscutting concerns running through service components that implements business logic in each layer. When business entities are modified, service components related to them should also be modified so that they can deal with those business entities with new types, even though their functionality remains the same. Our previous paper proposed what we call the DTT (Data Type-Tolerant) component model to efficiently process the variability of business entities, which are data externalized from service components. While the DTT component model, by removing direct coupling between service components and business entities, exempts the need to rewrite service components when business entities are modified, it incurs the burden of implementing data type converters that mediate between them. To solve this problem, this paper proposes a method to use ontology as the metadata of both SCDTs (Self-Contained Data Types) in service components and business entities, and a method to generate data type converter code using the ontology. This ontology-based DTT component model greatly enhances the reusability of service components and the efficiency in processing data variability by allowing the computer to automatically generate data type converters without error.

• Journal of Broadcast Engineering
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• v.20 no.3
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• pp.388-397
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• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.10
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• pp.127-136
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• 2007

It is easy to install and maintain a mobile multi-hop wireless network due to its self-organizing characteristics. However it has security weakness of the authentication of mobile multi-hop relay stations. Specially, the mobile multi-hop relay network in the IEEE 802.16j has the additional security weakness caused by the requirement of backward compatibility for mobile stations of the conventional IEEE 802.16 system. In this paper, we propose a novel mutual authentication scheme applicable to IEEE 802.16j-based mobile multi-hop relay network architecture. The scheme is able to resolve the initial trust gain problem of a multi-hop node at its entry to the network, the problem of rogue mobile multi-hop node and the problem of hop-by-hop authentication between multi-hop nodes. Effectively, the scheme is a hybrid scheme of the distributed authentication method and the centralized authentication method which have been considered to be deployed in the wireless ad-hoc network and the wireless network connected to wired authentication servers, respectively. Also, we analyze the effectiveness of the proposed hybrid authentication method.

• Journal of the Korea Concrete Institute
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• v.24 no.5
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• pp.567-575
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• 2012

A research was conducted to develop a 2-D nonlinear Galerkin finite element analysis of reinforced concrete structures subjected to high temperature with experiments. Algorithms for calculating the closed-form element stiffness for a triangular element with a fully populated material conductance are developed. The validity of the numerical model used in the program is established by comparing the prediction from the computer program with results from full-scale fire resistance tests. Details of fire resistance experiments carried out on reinforced concrete slabs, together with results, are presented. The results obtained from experimental test indicated in that the proposed numerical model and the implemented codes are accurate and reliable. The changes in thermal parameters are discussed from the point of view of changes of structure and chemical composition due to the high temperature exposure. The proposed numerical model takes into account time-varying thermal loads, convection and radiation affected heat fluctuation, and temperature-dependent material properties. Although, this study considered standard fire scenario for reinforced concrete slabs, other time versus temperature relationship can be easily incorporated.