• Title/Summary/Keyword: Computer I/O

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Development of Point of Production/Manufacturing Execution System to Manage Real-time Plant Floor Data (제품 실명제를 위한 POP/MES 시스템의 개발)

  • Gwon, Yeong-Do;Jo, Chung-Rae;Jeon, Hyeong-Deok
    • 연구논문집
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    • s.27
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    • pp.167-174
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    • 1997
  • Point of Production/Manufacturing Execution Systems are an essential component of operations in today's competitive business environments, which require greater production efficiency and effectiveness. POP/MES focuses on the valuing-adding processes, helping to reduce manufacturing cycle time, improve product quality, reduce WIP, reduce or eliminate paperwork between shifts, reduce lead time and empowering plant operations staff. In this paper, we implement POP/MES to manage real-time plant floor data which is gathered by I/O server into database management system. I/O server is a software allows data exchange between factory real-time database and several hardware devices such as PLC, DCS, robot and sensor through ethernet TCP/IP protocol.

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Design And Verification Of A PCI Express Behavioral Model Using C Language (C 언어를 이용한 PCI Express 동작 모델 설계 및 검증)

  • 예상영;현유진;성광수
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.811-814
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    • 2003
  • Today's and tomorrow's processors and I/O devices are demanding much higher I/O bandwidth than PCI 2.3 or PCI-X can deliver and it is time to engineer a new generation of PCI to serve as a standard I/O bus for future generation platforms. According to this demand the PCI SIG proposed PCI Express. This paper describes about the design of PCI Express Behavioral Model. A Behavioral Model enables the designers to test whether the design specifications are met by performing computer simulations rather than experiments on the physical prototype. In the proposed Model, we can verify whether our design concept satisfies the PCI Express functional protocol.

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New GGNMOS I/O Cell Array for Improved Electrical Overstress Robustness

  • Pang, Yon-Sup;Kim, Youngju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.65-70
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    • 2013
  • A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

Design of an Efficient In-Memory Journaling File System for Non-Volatile Memory Media

  • Hyokyung Bahn
    • International journal of advanced smart convergence
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    • v.12 no.1
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    • pp.76-81
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    • 2023
  • Journaling file systems are widely used to keep file systems in a consistent state against crash situations. As traditional journaling file systems are designed for block I/O devices like hard disks, they are not efficient for emerging byte-addressable NVM (non-volatile memory) media. In this article, we present a new in-memory journaling file system for NVM that is different from traditional journaling file systems in two respects. First, our file system journals only modified portions of metadata instead of whole blocks based on the byte-addressable I/O feature of NVM. Second, our file system bypasses the heavy software I/O stack while journaling by making use of an in-memory file system interface. Measurement studies using the IOzone benchmark show that the proposed file system performs 64.7% better than Ext4 on average.

Effect of Plasma Treatment on TiO2/TiO2-x Resistance Random Access Memory (플라즈마 표면처리가 TiO2/TiO2-x 저항 변화형 메모리에 미치는 영향)

  • Kim, Han-Sang;Kim, Sung-Jin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.6
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    • pp.454-459
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    • 2020
  • In this study, a TiO2/TiO2-x-based resistance variable memory was fabricated using a DC/RF magnetron sputtering system and ALD. In order to analyze the effect of oxygen plasma treatment on the performance of resistance random access memory (ReRAM), the TiO2/TiO2-x-based ReRAM was evaluated by applying RF power to the TiO2-x oxygen-holding layer at 30, 60, 90, 120, and 150 W, respectively. The ReRAM was fabricated, and the electrical and surface area performances were compared and analyzed. In the case of ReRAM without oxygen plasma treatment, the I-V curve had a hysteresis curve shape, but the width was very small, with a relatively high surface roughness of the oxygen-retaining layer. However, in the case of oxygen plasma treatment, the HRS/LRS ratio for the I-V curve improved as the applied RF power increased; stable improvement was also noted in the surface roughness of the oxygen-retaining layer. It was confirmed that the low voltage drive was not smooth due to charge trapping in the oxygen diffusion barrier layer owing to the high intensity ReRAM applied with an RF power of approximately 150 W.

Analysis of Performance for Computer System using BCMP Queueing Net work with Priority Levels (우선순위를 고려한 BCMP 큐잉 네트워크를 이용한 컴퓨터 시스템의 성능 분석)

  • Park, Dong-Jun;Lee, Sang-Hun;Jeong, Sang-Geun
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.1
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    • pp.191-199
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    • 1996
  • In this paper, We assume that the closed computer system model composed of multiprocessor system is analyzed by BCMP queueing network theory with priority levels. In this system that contains terminals, processors and I/O devices, We show maximum throughput and the number of active terminals in the optimum multiprogramming levels. It is compared the performance with the other. In the result, it is obtained the optimum number of processors and active terminals. Therefore, the system model consisted of the optimum number of processor and multiprogramming level m is analyzed by the servers with a priority level. Each server is applied to the type of server which is characterized terminal, processor I/O device etc.. This model is analyzed by the server with a probability ditribution. Ideal state is proposed by the modeling for priority levels. Finally, we try to increase the performance in overload system.

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Design and Implementation of Hybrid Hard Disk I/O System based on n-Block Prefetching for Low Power Consumption and High I/O Performance (저전력과 입출력 성능이 향상된 n-블록 선반입 기반의 하이브리드 하드디스크 입출력 시스템 설계 및 구현)

  • Yang, Jun-Sik;Go, Young-Wook;Lee, Chan-Gun;Kim, Deok-Hwan
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.6
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    • pp.451-462
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    • 2009
  • Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

A Study on Information Block Sort Algorithm (정보 블록 정렬 알고리즘에 관한 연구)

  • Song, Tae-Ok
    • The Journal of Korean Association of Computer Education
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    • v.6 no.3
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    • pp.1-8
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    • 2003
  • In this paper, I proposed a sort algorithm named Information Block Sort Algorithm(IBSAl which is not influenced on distribution of data in the list and has time complexity of O(NlogN). Also I evaluated the IBSA using a simulator. Performance analysis shows that, in case of sorting randomly generated two millions data, the number of actual comparisons has taken place about 36% of the number of comparisons in the improved Quick sort algorithm and 22% in Quick sort algorithm.

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The Hardware Side of Development of a 16 Bit Computer System (IEEE 796 Bus를 이용한 16 Bit 마이크로컴퓨터 시스템의 하드웨어 개발)

  • 정용우;박기호
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.6
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    • pp.33-36
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    • 1983
  • This paper briefly describes the hardware side of "Development of a 16 bit computer system, " one of the national projects in which Samsung Semiconductor Telecommunication Inc. '||'&'||' KIET combined their efforts to develop a 16 bit microcomputer system based on IEEE 796 hardware bus structure. In the project CPU, memory and I/O controller boards were developed, tested and integrated into a complete system.m.

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A Research of Extension Buffer Cache Management used Nand- flash based SSD (Nand-Flash 기반의 SSD를 이용한 확장 버퍼 캐쉬 관리 기법 연구)

  • Oh, Kyung-Hwan;Bong, Sun-Jong;Kim, Kyung-Tae;Youn, Hee-Young
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2014.07a
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    • pp.235-236
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    • 2014
  • 플래시 메모리 기술이 발전함에 따라 낸드 플래시 기반의 SSD가 상용화 되면서 I/O시간을 줄이기 위한 연구들이 진행되고 있다. 이에 본 논문에서는 기존의 메인 메모리와 저장장치 사이에 확장 버퍼 캐시로써 SSD를 사용하고 메인 메모리에서 방출 된 페이지들을 구분하여 같은 성향의 페이지들을 블록화 하는 모델을 제안한다. 이러한 모델을 통하여 블록 단위로 사용되는 SSD를 효율적으로 이용하여 읽기 및 쓰기 성능을 높이고 I/O에 해당하는 시간들을 줄임으로써 전체적인 성능 향상을 증명하였다.

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