• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.244-246
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• 2001

In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.2
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• pp.93-99
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• 2013

Fractal theory has been adopted as an effective tool for modelling complex and irregular natural phenomena facing in the fields of Computer Science, Engineering, Medical, Climatology and so on. In this paper, we presents an algorithm which enhances the performance of the triangular prism method(TPM) which has been widely used for fractal dimension extraction of natural terrains and images. For this, existing sampling methods are analyzed and a new sampling method which takes their merits is proposed. The effectiveness of the proposed algorithm is tested on fractal terrain maps and its performance is compared with that of other methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.62-71
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• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• Structural Engineering and Mechanics
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• v.51 no.5
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• pp.793-808
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• 2014

The goal of this study is to evaluate and design steel plates with optimal material distributions achieved through a specific material topology optimization by using a CCARAT (Computer Aided Research Analysis Tool) as an optimizer, topologically optimally updating node densities as design variables. In typical material topology optimization, optimal topology and layouts are described by distributing element densities (from almost 0 to 1), which are arithmetic means of node densities. The average element densities are employed as material properties of each element in finite element analysis. CCARAT may deal with material topology optimization to address the mean compliance problem of structural mechanical problems. This consists of three computational steps: finite element analysis, sensitivity analysis, and optimality criteria optimizer updating node densities. The present node density based design via CCARAT using node densities as design variables removes jagged optimal layouts and checkerboard patterns, which are disadvantages of classical material topology optimization using element densities as design variables. Numerical applications that topologically optimize reinforcement material distribution of steel plates of a cantilever type are studied to verify the numerical superiority of the present node density based design via CCARAT.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.4
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• pp.29-35
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• 2014

The formula contains up between the text and the structural information, as well as their mathematical symbols. Research on-line or off-line recognition formula is underway actively used in various fields, and various forms of the equation are implemented recognition system. Although many documents are included in the various formulas, it is not easy to enter a formula into the computer. Recognition of the expression is divided into two processes of symbol recognition and structural analysis. After analyzing the location information of each character is specified to recognize the effective area after each symbol, and to the structure analysis based on the proximity between the characters is recognized as an independent single formula. Furthermore, analyzing the relationship between the front and back each time a combination of the position relationship between each symbol, and then to add the symbol which was able to easily update the structure of the entire formula. In this paper, by using a scanner to scan the book formula was used to interpret the meaning of the recognized symbol has a relative size and location information of the expression symbol. An algorithm to remove the formulas for calculation of the number of formula is present at the same time is proposed. Using the proposed algorithms to scan the books in the formula in order to evaluate the performance verification as 100% separation and showed the recognition rate equation.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1171-1176
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• 2023

In this paper, we predicts the estimated price using the DNBP (Deep learning Network to predict Budget Price) model with bidding data obtained from the bidding websites, ElecNet and OK EMS. We use the DNBP model to predict four lottery preliminary price, calculate their arithmetic mean, and then estimate the expected budget price ratio. We evaluate the model's performance by comparing it with the actual expected budget price ratio. We train the DNBP model by removing some of the 15 input nodes. The prediction results showed the lowest RMSE of 0.75788% when the model had 6 input nodes (a, g, h, i, j, k).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.