• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.4
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• pp.878-894
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• 2013

Secure multimedia multicast applications involve group communications where group membership requires secured dynamic key generation and updating operations. Such operations usually consume high computation time and therefore designing a key distribution protocol with reduced computation time is necessary for multicast applications. In this paper, we propose a new key distribution protocol that focuses on two aspects. The first one aims at the reduction of computation complexity by performing lesser numbers of multiplication operations using a ternary-tree approach during key updating. Moreover, it aims to optimize the number of multiplication operations by using the existing Karatsuba divide and conquer approach for fast multiplication. The second aspect aims at reducing the amount of information communicated to the group members during the update operations in the key content. The proposed algorithm has been evaluated based on computation and communication complexity and a comparative performance analysis of various key distribution protocols is provided. Moreover, it has been observed that the proposed algorithm reduces the computation and communication time significantly.

• Proceedings of the KOSOMBE Conference
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• v.1991 no.05
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• pp.5-7
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• 1991

We have developed an efficient and robust image reconstruction algorithm for static impedance imaging. This improved Newton-Raphson method produced more accurate images by reducing the undesirable effects of the ill-conditioned Hessian matrix. We found that our electrical impedance tomography (EIT) system could produce two-dimensional static images from a physical phantom with 7% spatial resolution at the center and 5% at the periphery. Static EIT image reconstruction requires a large amount of computation. In order to overcome the limitations on reducing the computation time by algorithmic approaches, we implemented the improved Newton-Raphson algorithm on a parallel computer system and showed that the parallel computation could reduce the computation time from hours to minutes.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.639-642
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• 2005

Motion Estimation(ME) is an important part of video compression, because it requires a large amount of computation. Half-pixel and quarter-pixel motion estimation allows high video compression rates but it also has high computation complexity. In this paper we suggest a new and efficient motion estimation algorithm for half-pixel and quarter-pixel motion estimation using SAD values. In the method, an integer-pixel motion vector is found and then only three neighboring points of the integer-pixel motion vector is evaluated to find the half-pixel motion vector. The quarter-pixel motion vector is also found by using a similar method. Experimental results of our method shows 20% reduction in computation time, when compared with those of a conventional method, while producing same quality motion vectors.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.68-70
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• 1996

In this paper, an efficient parallel computation method for solving large sparse systems of linear algebraic equations by using Cholesky's method in the finite element method is studied. The methods of minimizing the number of fill-ins in the factorization process of factorization are investigated for minimizing the amount of memory and computation time. The parallel programming is implemented under the PVM(Parallel Virtual Machine) environment. The method of load-distribution is studied for minimizing the computation time and the communication time.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1167-1174
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• 1999

In this paper, we present a new technique for the local decomposition of convex structuring elements for morphological image processing. Local decomposition of a structuring element consists of local structuring elements, in which each structuring element consists of a subset of origin pixel and its eight neighbors. Generally, local decomposition of a structuring element reduces the amount of computation required for morphological operations with the structuring element. A unique feature of our approach is the use of linear integer programming technique to determine optimal local decomposition that guarantees the minimal amount of computation. We defined a digital convex polygon, which, in turn, is defined as a convex structuring element, and formulated the necessary and sufficient conditions to decompose a digital convex polygon into a set of basis digital convex polygons. We used a set of linear equations to represent the relationships between the edges and the positions of the original convex polygon, and those of the basis convex polygons. Further. a cost function was used represent the total processing time required for computation of dilation/erosion with the structuring elements in a decomposition. Then integer linear programming was used to seek an optimal local decomposition, that satisfies the linear equations and simultaneously minimize the cost function.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2005.04a
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• pp.317-324
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• 2005

Korean shipyards have accumulated a great amount of data. But they do not have appropriate tools to utilize the data in practical works. Engineering data contains experts' experience and know-how In its own. It is very useful to extract knowledge or information from the accumulated existing data by using datamining technique. This paper treats an evolutionary computation method based on genetic programming (GP), which can be one of the components to realize datamining.

• Proceedings of the KSPS conference
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• 2006.11a
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• pp.88-91
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• 2006

Steered response power(SRP) based algorithm uses a focused beamformer which steers the array to various locations and searches for a peak in output power to localize sound sources. SRP-PHAT, a phase transformed SRP, shows high accuracy, but requires a large amount of computation time. This paper proposes an algorithm that clusters search spaces in advance to reduce computation time of SRP based algorithms.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.989-990
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• 2006

This paper presents a design of 3D Graphics Geometry processor. A geometry processor needs to cope with a large amount of computation and consists of transformation processor and lighting processor. To deal with the huge computation, a vector processing structure based on pipeline chaining is proposed. The proposed geometry processor performs 4.3M vertices/sec at 100MHz using 11 floating-point units.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.848-855
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• 1989

By structural comparison of process optimization strategies based on Simultaneous Modular Approach, they can be classified into two groups : the Sequential Module Based Approach and the Two-Tier Approach. The Sequential Module Based Approach needs rigorous models and a set of accurate solutions are guranteed. However, it requires large amount of computation time. In the Two-Tier Approach composed of rigorous and simplified models, optimization calculation uses simplified models, therefore comparatively smaller amount of computation time is required but the obtained solutions may not be accurate. These optimization problems were somewhat improved by the alternate application of the two strategies. In this study, improved optimization strategy is suggested, in which Jacobian Matrix is modified to accomodate the strong points of above mentioned strategies. The results of case study show that this approach is superior to the other strategies.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.15-24
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• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.