• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.151-160
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• 2005

In this paper, we propose a new fast motion estimation algorithm based on successive elimination algorithm (SEA) which can dramatically reduce heavy complexity of the variable block size motion estimation in H.264 encoder. The proposed method applies the conventional SEA in the hierarchical manner to the seven block modes. That is, the proposed algorithm can remove the unnecessary computation of SAD by means of the process that the previous minimum SAD is compared to a current SAD for each mode which is obtained by accumulating sum norms or SAD of $4\times4$ blocks. As a result, we have tighter bound in the inequality between SAD and sum norm than in the ordinary SEA. If the basic size of the block is smaller than $4\times4$, the bound will become tighter but it also causes to increase computational complexity, specifically addition operations for sum norm. Compared with fast full search algorithm of JM of H.264, our algorithm saves 60 to $70\%$ of computation on average for several image sequences.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3132-3138
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• 2014

In many communication systems, intersymbol interference, DC and impulsive noise are hard-to-solve problems. For the purpose of cancelling such interferences, the concept of lagged cross-correlation of probability has been used for blind equalization. However, this algorithm has a large burden of computation. In this paper, a recursive method of the algorithm based on the lagged probability correlation is proposed. The summation operation in the calculation of gradient of the cost is transformed into a recursive gradient calculation. The recursive method shows to reduce the high computational complexity of the algorithm from O(NM) to O(M) for M symbols and N block data having advantages in implementation while keeping the robustness against those interferences. From the results of the simulation, the proposed method yields the same learning performance with reduced computation complexity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1287-1296
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• 2009

It is very important to estimate the Signal to Noise Ratio(SNR) of received signal in time varying channel state. Most SNR estimation techniques derive the SNR estimates solely from the samples of the received signal after the matched filter. In the severe distorted wireless channel, the performance of these estimators become unstable and degraded. LP-based SNR estimator which can operate on data samples collected at the front-end of a receiver shows more stable performance than other SNR estimator. In this paper, we study an efficient SNR estimation algorithm based on LP and propose a new estimation method to decrease the computation complexity. Proposed algorithm accomplishes the SNR estimation process efficiently because it uses the forward prediction error and its conjugate value during the linear prediction error update. Via the computer simulation, the performance of this proposed estimation method is compared and discussed with other conventional SNR estimators in digital communication channels.

• The Journal of the Acoustical Society of Korea
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• v.31 no.7
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• pp.427-434
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• 2012

The overlap-add technique based on waveform similarity (WSOLA) method is known to be an efficient high-quality algorithm for time scaling of speech signal. The computational load of WSOLA is concentrated on the repeated normalized cross-correlation (NCC) calculation to evaluate the similarity between two signal waveforms. To reduce the computational complexity of WSOLA, this paper proposes a fast NCC computation method, in which NCC is obtained through pre-calculated sum tables to eliminate redundancy of repeated NCC calculations in the adjacent regions. While the denominator part of NCC has much redundancy irrespective of the time-scale factor, the numerator part of NCC has less redundancy and the amount of redundancy is dependent on both the time-scale factor and optimal shift value, thereby requiring more sophisticated algorithm for fast computation. The simulation results show that the proposed method reduces about 40%, 47% and 52% of the WSOLA execution time for the time-scale compression, 2 and 3 times time-scale expansions, respectively, while maintaining exactly the same speech quality of the conventional WSOLA.

• Journal of IKEEE
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• v.24 no.3
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• pp.783-790
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• 2020

In this paper, the human detecting radar system for indoor security applications is proposed, and its FPGA-based implementation results are presented. In order to minimize the complexity and memory requirements of the computation, the top half of the spectrogram was used to extract features, excluding the feature extraction techniques that require complex computation, feature extraction techniques were proposed considering classification performance and complexity. In addition, memory requirements were minimized by designing a pipeline structure without storing the entire spectrogram. Experiments on human, dog and robot cleaners were conducted for classification, and 96.2% accuracy performance was confirmed. The proposed system was implemented using Verilog-HDL, and we confirmed that a low-area design using 1140 logics and 6.5 Kb of memory was possible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1237-1242
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• 2007

In this paper, we study STBC(Space Time Block Code) detection scheme in time varying Rayleigh fading channel. When the channel is varying during the time duration of STBC, the channel matrix of orthogonal STBC is not orthogonal. To get the optimum reception performance in this channel, joint ML detection scheme may be used, however this scheme requires high computation complexity. Decision feedback scheme is proposed to reduce the computation complexity with less reception performance. In this paper, we propose a novel STBC detection algorithm using double decision feedback which is less complex than the joint ML scheme and outperforms the conventional decision feedback scheme.

• Journal of KIISE:Software and Applications
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• v.33 no.4
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• pp.411-417
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• 2006

Motion Estimation (ME) is an important part of video coding process and it takes the largest amount of computation in video compression. Half-pixel and quarter-pixel motion estimation can improve the video compression rate at the cost of higher computational complexity In this paper, we suggest a new efficient low-complexity algorithm for half-pixel and quarter pixel motion estimation. It is based on the experimental results that the sum of absolute differences(SAD) shows parabolic shape and thus can be approximated by using interpolation techniques. The sub-pixel motion vector is searched from the minimum SAD integer-pixel motion vector. The sub-pixel search direction is determined toward the neighboring pixel with the lowest SAD among 8 neighbors. Experimental results show that more than 20% reduction in computation time can be achieved without affecting the quality of video.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.74-79
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• 2008

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes fast fractional search algorithms by combining the SASR(Simplified Adaptive Search Range) and the MSDSP(Mixed Small Diamond Search Pattern) with the predicted fractional motion vector. Compared with the full search and the prediction-based directional fractional pixel search, the proposed algorithms can reduce up to 93.2% and 81% of fractional search points, respectively with the maximum PSNR lost less than 0.04dB. Therefore, the proposed fast search algorithms are quite suitable for mobile applications requiring low power and complexity.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1C
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• pp.9-15
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• 2007

We propose the fast full search algorithm that reduces the computation of the block matching algorithm which is used for motion estimation of the video coding. Since the conventional spiral search method starts searching at the center of the search window and then moves search point to estimate the motion vector pixel by pixel, it is good for the slow motion pictures. However the proposed method is good for the fast and slow motion because it estimates the motion in the new search order after partitioning the search window. Also, when finding the motion vector, this paper presents the method that reduces the complexity by computing the matching error in the order which is determined by local image complexity. The proposed algorithm reduces the computation up to 99% for block matching error compared with the conventional spiral full search algorithm without any loss of image quality.