• Journal of the Korean Society of Marine Environment & Safety
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• v.29 no.7
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• pp.902-909
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• 2023

This study evaluated the performance test of a small-sized LTE-Maritime(LTE-M) transceiver that was developed and promoted to expand the use of intelligent maritime traf ic information services led by the Ministry of Oceans and Fisheries with the aim of supporting the prevention of maritime accidents. Accoriding to statistics, approximately 30% of all marine accidents in Korean water occur with ships weighing less than 3 tons. Therefore, the blind spots of maritime safety must be supplemented through the development of small-sized transceivers. The small transceiver may be used in fishing boats that are active near coastal waters and in water leisure equipment near the coastline. Therefore, verifying whether sufficient performance and stable communication quality are provided is necessary, considering the environment of their real usage. In this study, we reviewed the communication quality goals of the LTE-M network and the performance requirements of small-sized transceivers suggested by the Ministry of Oceans and Fisheries, and proposed a test plan to appropriately evaluate the performance of small-sized transceivers. The validity of the proposed test method was verified for six real-sea areas with a high frequency of marine accidents. Consequently, the downlink and uplink transmission speeds of the small-sized LTE-M transceiver showed performances of 9 Mbps or more and 3 Mbps or more, respectively. In addition, using the coverage analysis system, coverage of more than 95% and 100% were confirmed in the intensive management zone (0-30 km) and interesting zone (30-50 km), respectively. The performance evaluation method and test results proposed in this paper are expected to be used as reference materials for verifying the performance of transceivers, contributing to the spread of government-promoted e-navigation services and small-sized transceivers.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.