• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.9
• /
• pp.827-832
• /
• 2011

Communication is very important in warfare. Dispatch riders were used in ancient warfare, but communication system is used in modern warfare, as the advancement of communication equipments. In order to weaken enemy military strength, communication jamming signal disrupts enemy communication systems. Tone jamming is one of the common communication jamming techniques. Tone jamming is that several tones are placed in the spectrum for neutralizing the enemy's radio communication receivers. In this paper, we develop multitone jamming signal controlled tone number up to 10 tones and tone interval between tones using DDS(Direct Digital Synthesizer) core and FPGA(Field Programmable Gate Arry) of Xilinx Inc. and show the jamming signal output.

• Journal of Drive and Control
• /
• v.12 no.4
• /
• pp.35-40
• /
• 2015

A gas spring provides support force for lifting, positioning, lowering, and counterbalancing weights. It offers a wide range of reaction force with a flat force characteristic, simple mounting, compact size, speed controlled damping, and cushioned end motion. The most common usage is as a support on a horizontally hinged automotive tail gate. However, its versatility and ease of use has been applied in many other industrial applications ranging from office equipment to off-road vehicles. The cylinder of a gas spring is filled with compressed nitrogen gas, which is applied with equal pressure on both sides of the piston. The surface area of the rod side of the piston is smaller than the opposite side, producing a pushing force. The magnitude of the reaction force is determined by the cross-sectional area of the piston rod and the internal pressure inside the cylinder. The reaction force is influenced by many design parameters such as initial chamber volume, diameter ratio, etc. In this paper, we investigated the reaction force characteristics and carried out parameter sensitivity analysis for the design parameters of a gas spring.

• Journal of electromagnetic engineering and science
• /
• v.14 no.2
• /
• pp.68-73
• /
• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• Journal of Power Electronics
• /
• v.10 no.4
• /
• pp.342-350
• /
• 2010

Randomizing the switching frequency (RSF) to reduce the electromagnetic interference (EMI) of switching power converters is a well-known technique that has been previously discussed. The randomized pulse position (RPP) technique, in which the switching frequency is kept fixed while the pulse position (the delay from the starting of the switching cycle to the turn-on instant within the cycle) is randomized, has been previously addressed in the literature for the same purpose. This paper presents a double-hybrid technique (DHB) for EMI reduction in dc-dc switching regulators. The proposed technique employed both the RSF and the RPP techniques. To effectively spread the conducted-noise frequency spectrum and at the same time attain a satisfactory output voltage quality, two parameters (switching frequency and pulse position) were randomized, and a third parameter (the duty ratio) was controlled by a digital compensator. Implementation was achieved using field programmable gate array (FPGA) technology, which is increasingly being adopted in industrial electronic applications. To evaluate the contribution of the proposed DHB technique, investigations were carried out for each basic PWM, RPP, RSF, and DHB technique. Then a comparison was made of the performances achieved. The experimentally investigated features include the effect of each technique on the common-mode, differential-mode, and total conducted-noise characteristics, and their influence on the converter’s output ripple voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.451-454
• /
• 2015

This paper introduces 3 type of OTAs with $0.35-{\mu}m$ standard CMOS technology for Low-Power, Low-Voltage. The first type is a two-stage OTA designed to operate with a 1-V VDD and it has $1.774{\mu}W$ low power consumption. All transistors are operating in strong inversion. It takes Gm-Enhancement techniques to compensate gm, which is lowered by Bulk-Driven technique and has an Wide swing current mirror for low voltage operation and a Class-A output. The second type is a Two-stage OTA designed to operate with a 0.8-V VDD and It has 52nW low power consumption and 112dB high gain. The current mirror uses Composite Transistor binding Gates of two MOSFET to raise Rout which is similar with cascode structure. The third type is a Two-stage OTA designed to operate with a 0.6-V VDD and It has 160nW low power consumption and 72dB high gain. It takes Level Shift technique by Common Gate structure to amplify signals without additional bias voltage at second stage.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.7 s.361
• /
• pp.41-46
• /
• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.567-568
• /
• 2008

In this paper, we proposed the design on LNA for $3{\sim}5\;GHz$ frequency with Using $0.18{\mu}m$CMOS technology. The LNA gain is 12-15 dB, and noise figure is lower than 5 dB and Input/output matching is lower than 10 dB in frequency range from 3 GHz to 5 GHz. The topology, which common source output of cascode is reduced noise figure and improved gain. Input common gate amplifier extend LNA's bandwidth.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.818-823
• /
• 2014

A high-gain wideband low noise amplifier (LNA) using $0.25-{\mu}m$ Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of $25.1{\pm}0.8dB$ and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.10
• /
• pp.2045-2051
• /
• 2009

A 5-GHz band Low Noise Amplifier(LNA) using SOI MOSFET is designed. To improve the noise performance, depletion-type SOI MOSFET is adopted, and it is designed by the two-stage topology consisting of common-source and common-gate stages for low-voltage operation. The fabricated LNA achieved an S11 of less than -10dB, voltage gain of 21dB with a power consumption of 8.3mW at 5.5GHz, and a noise figure of 1.7dB indicated that the depletion-type LNA improved the noise figure by 0.3dB compared with conventional type. These results show the feasibility of a CMOS LNA employing depletion-type SOI MOSFET for low-noise application.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.20 no.2
• /
• pp.63-74
• /
• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.