• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.5 s.96
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• pp.482-487
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• 2005

In this paper, we propose the control method of output impedance of each cascode unit cell of distributed amplifier by connecting varactors in the gate-terminal of common gate. Compared to common source unit cell, cascode unit cell has many advantages such as high gain and high output impedance as well as negative resistance loading. But if the transistor model which is used in design is inaccurate and process parameter is changed, oscillation sometimes can occur at band edge in which the gain start to drop. Therefore, we need control circuit which can prevent oscillation, although the circuit has already fabricated, and varactor connected to gate-terminal of common gate of cascode gain cell can play that part. Measured result of fabricated distributed amplifier shows the capability of contol of gain characteristic by adjusting of value of varactors, this can guarantee the stability of the circuit. The gain is $8.92\pm0.82dB$ over 49 GHz, the group delay is $\pm9.3 psec$ over 41 GHz. All transistor which has $0.15{\mu}m$ gate length is GaAs based p-HEMT, and distributed amplifier is put together with 4 stages.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Journal of Drive and Control
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• v.12 no.4
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• pp.15-20
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• 2015

Unlike a typical metal spring, a gas spring uses compressed gas contained in a cylinder and compressed by a piston to exert a force. A common application includes automobiles where gas spring are incorporated into the design of open struts that support the weight of tail gate. They are also used in furniture such as office chairs, and in medical and aerospace applications. The gas spring works by the application of pressurized gas (nitrogen) contained in a cylinder. The internal pressure of the gas spring greatly exceeds atmospheric pressure. This differential in pressure exists at any rod position and generates an outward force on the rod, making the gas spring extend. In this paper, we investigated the dynamic characteristics of a gas spring on an automotive tail gate system.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.215-226
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• 2004

This study develops a improved gate assignment algorithm and decision support system using its algorithm to extract a assignment result minimizing a walking distance of passengers in airport and maximizing the utilization rate of avaliable gates in domestic airports. By operation support system, it may contribute greatly in efficient enlargement of airport operation and increase the airport reliability through quickly coping with takeoff and landing delay of flight due to weather change, preservation and repair of gate, etc. Also, passengers who use airport terminal can minimize time and walking distance for departure, arrival, and transit, and it may greatly reduce the additional operation cost for common gates through maximizing the utilization rate for exclusive usage gates for airplanes which use gates.

• Proceedings of the Safety Management and Science Conference
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• 2004.11a
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• pp.221-227
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• 2004

This study develops a improved gate assignment algorithm and decision support system using its algorithm to extract a assignment result minimizing a walking distance of passengers in airport and maximizing the utilization rate of avaliable gates in domestic airports. By operation support system, it may contribute greatly in efficient enlargement of airport operation and increase the airport reliability through quickly coping with takeoff and landing delay of flight due to weather change, preservation and repair of gate, etc. Also, passengers who use airport terminal can minimize time and walking distance for departure, arrival, and transit, and it may greatly reduce the additional operation cost for common gates through maximizing the utilization rate for exclusive usage gates for airplanes which use gates.

• Journal of the Korean Institute of Rural Architecture
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• v.16 no.3
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• pp.27-36
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• 2014

The purpose of this study is to provide necessary information for the establishment of remodeling range needed first to support the future remodeling of rural housing. For this, this study examined landscape characteristics of rural housing such as an outer wall, a roof, a fence, and a gate which are main elements of forming the landscape of a rural village and rural residents' perception for remodeling. The results were as follows. The subject rural housing mostly had a timber structure and a masonry structure. Common roof types were a hip-and-gable roof and a gable roof. Frequent materials were a panel, a tile, and slate and common colors were primary colors such as reddish brown, black, and gray. A fence made of cement blocks and finished by a white paint was often found. A closed gate with iron frames was common. A standup kitchen and a flush toilet inside the house were common. The family members of rural residents were mostly two including a farmer husband and his wife. Elderly people of sixty and over were the most common. For residential environment satisfaction, a half of respondents were not unsatisfied with residential environment mostly due to an old house. Most respondents who were not satisfied with residential environment had high perception for the need of remodeling. The most commonly asked remodeling part was a roof, followed by a toilet, and an outer wall, indicating that the need of exterior remodeling was higher than that of interior remodeling. For a remodeling method, a total improvement was preferred. Although some rural village housing was improved by support of the government, local governments, or social groups, there are still many old houses. As this co-existence of improved houses and old houses hinders the landscape of rural village, it is necessary to give a support. But rural residents' requests should be first actively reflected to establish a guideline of supporting rural house remodeling.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.369-372
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• 1999

In this paper, we propose a new method for power estimation in nodes of multi-level combinational circuits and describe its application to the extraction of common expressions for low power design. It is assumed that each node is implemented as a complex gate and the capacitance and the switching activity of the nodes are considered in the power estimation. Extracting common expressions which is accomplished mostly by the extraction of kernels, can be transformed to the problem of rectangle covering. We describe how the newly proposed estimation method can be applied to the rectangle covering problem and show the experimental results with comparisons to the results of SIS-1.2.

• Korean Institute of Interior Design Journal
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• v.17 no.5
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• pp.72-79
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• 2008

Nagaya is one of the traditional Japanese housing types in which multiple houses are attached together. In Nagaya, walls are shared by several houses but entrances are privately owned by houses. Nagaya consists of many wooden houses for common people located in parallel with narrow alleys between them. Nagaya was one of the representative housing types in Japanese architectural history. This research is to study the background of the origination of Nagaya in Japan, the characteristics of space and land planning, the features and causes of the changes in the space and land planning. In this research, we observed and analyzed unit plans of a block of gate-type Nagayas in Hanan, Osaka. The results are as follows. First, as the inner alleys(Roji) are closed, the number of entrances to each housing lot decreased from two to one since one entrance that used to be open to inner alleys(Roji) are permanently closed. Second, walls between streets and housing lots which used to be one of the outstanding characteristics of gate-type Nagayas are disappearing. Third, as the bathrooms are added to houses, the front gardens are being degraded to empty spaces or sometimes totally removed. Fourth, the space in the first floor of houses become family spaces, and that in the second floor is divided into private rooms for individuals.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.