• Bulletin of the Korean Mathematical Society
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• v.54 no.4
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• pp.1421-1441
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• 2017

We compute explicitly the matrix represented by the Toeplitz operator on the Hardy space over a smoothly finitely connected bounded domain in the plane with respect to special orthonormal bases consisting of the classical kernel functions for the space of square integrable functions and for the Hardy space. The Fourier coefficients of the symbol of the Toeplitz operator are obtained from zeroth row vectors and zeroth column vectors of the matrix. And we also find some condition for the product of two Toeplitz operators to be a Toeplitz operator in terms of matrices.

• Communications for Statistical Applications and Methods
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• v.12 no.1
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• pp.199-205
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• 2005

In general, simple correspondence analysis has handled mainly correspondence relations between the row and column categories but can not display the trends of their change over the time. For solving this problem, we will propose DSCA(Dynamic Simple Correspondence Analysis) of transition matrix data using supplementary categories in this study, Moreover, DSCA provides its trend of the change for the future by predicting and displaying trend toward the change from a standard point of time to the next.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.93-98
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• 1991

An improved and flexible matrix algorithm for solving interlinked separation problems which is based on the homotopy continuation method has been developed. A flexible model of the interlinked stream in standardized matrix form and JACOBIAN generation I algorithm for homotopy continuation are suggested. Also DOF analysis is performed for easy-understanding of equation based simulation of complex column systems. The Algorithm is tested on several problems of interlinked separation processes and some of results are documented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.70-77
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• 1984

This paper represents a fast computational algorithm for the discrete sine transform defined by Kekre and Solanki. Techniques are developed to factor the discrete sine trans form matrix into M=log2 2N matrices, where the number(N) of sampled data points is a power of two. Each factorial matrix contains not more than two non-zero real elem tints in any row or column. As a result of this method, the exact a배orithm for the fast discrete sine transform is accomplished. The algorithm is illustiated by a signal flow graph, which may be readily translated to hardware or software implementation.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.10a
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• pp.289-292
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• 1996

In Cholesky factorization of the interior point method, dense columns of A matrix make dense Cholesky factor L regardless of sparsity of A matrix. We introduce a method to transform a primal problem to a dual problem in order to preserve the sparsity.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.737-741
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• 2009

This paper addresses the factorization method to estimate the projective structure of a scene from feature (points) correspondences over images with occlusions. We propose both a column and a row space approaches to estimate the depth parameter using the subspace constraints. The projective depth parameters are estimated by maximizing projection onto the subspace based either on the Joint Projection matrix (JPM) or on the the Joint Structure matrix (JSM). We perform the maximization over significant observation and employ Tardif's Camera Basis Constraints (CBC) method for the matrix factorization, thus the missing data problem can be overcome. The depth estimation and the matrix factorization alternate until convergence is reached. Result of Experiments on both real and synthetic image sequences has confirmed the effectiveness of our proposed method.

• Journal of Korea Multimedia Society
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• v.7 no.6
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• pp.781-790
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• 2004

This paper presents a fourth-order cumulants based iterative algorithm for blind channel equalization. It is robust with respect to the existence of heavy Gaussian noise in a channel and does not require the minimum phase characteristic of the channel. In this approach, the transmitted signals at the receiver are over-sampled to ensure the channel described by a full-column rank matrix. It changes a single-input/single-output (SISO) finite-impulse response (FIR) channel to a single-input/multi-output (SIMO) channel. Based on the properties of the fourth-order cumulants of the over-sampled channel outputs, the iterative algorithm is derived to estimate the deconvolution matrix which makes the overall transfer matrix transparent, i.e., it can be reduced to the identity matrix by simple reordering and scaling. Both a closed-form and a stochastic version of the proposed algorithm are tested with three-ray multi-path channels in simulation studies, and their performances are compared with a method based on conventional second-order cumulants. Relatively good results are achieved, even when the transmitted symbols are significantly corrupted with Gaussian noise.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.