• Current Industrial and Technological Trends in Aerospace
• /
• v.8 no.1
• /
• pp.77-85
• /
• 2010

The current GPS constellation consists of 32 Block IIA/IIR/IIR-M satellites including 12 Block IIA satellites on service over 15 years. The satellites in poor space conditions may suffer from anomalies, especially influenced by aging atomic clocks which are of importance positioning and timing. Recently, the IGS Ultra-rapid predicted products have not shown acceptably high quality prediction performance because the Block IIA cesium clocks may be easily affected by various factors such as temperature and environment. The anomalies of aging clocks involve lower performance of positioning in the GPS applications. We, thus, describe satellite clock behaviors and anomalies induced by aging clocks and their detection technologies to avoid such anomalies.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.7C
• /
• pp.608-615
• /
• 2007

Generally time of arrival (TOA) information via two way communications can be derived by accurate round trip time (RTT) between two devices. However, response time demanded in RTT measurement is long, a serious TOA error is caused by each different clock drift between two devices. In order to solve this problem, we propose the TOA and time difference of arrival (TDOA) estimation scheme with mitigating clock drift effect. To verify the performance of proposed method, we compared the proposed scheme with one way based TDOA acquisition method introduced by IEEE 802.15.4a Task Group and then we could conclude that the proposed method has better performance over other methods.

• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.289-292
• /
• 2004

In this paper, we propose parallel Viterbi decoders applied to UWB(Ultra Wide Band). In consideration of power dissipation and ease of design, we design the architecture, using 132MHz clock instead of 528MHz clock in Baseband. Because Deinterleaver writes and reads the transmitted data per 6Ncbps(The number of coded bits per symbol). using the difference between the number of sampling clock per symbol and the number of coded bits per symbol, we reduce performance degradation of parallel Viterbi decoders. In comparison with using 528MHz clock, the result is little difference.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.12
• /
• pp.61-67
• /
• 2005

This paper presents the carrier phase DGPS method providing a stable navigation solution under the condition of frequent blockage of the GPS signals. The proposed algorithm reject the channels having large errors using a clock bias drift and then calculated the more accurate solution. By investigating the relation between visible satellites` elevation and their clock bias drift, a proper threshold is set. Simulation shows that the presented result is as good as that of commercial system with real data.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.5
• /
• pp.1351-1361
• /
• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

• Journal of Positioning, Navigation, and Timing
• /
• v.12 no.3
• /
• pp.215-228
• /
• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.9
• /
• pp.1343-1349
• /
• 2013

In optical fiber communications, several newly-developed signal formats are used to obtain the best performance within limited spectral bandwidth. CSRZ (carrier-suppressed return-to-zero) format is one of the new signal formats, which has better spectral efficiency and better robustness to dispersion than RZ (return-to-zero) format. Thus it is widely used for demonstrating high-speed optical communication systems. In an earlier research, we proposed a clock-extraction method of CSRZ signal to monitor chromatic dispersion. However, the clock-frequency component extracted by the clock-extraction method can be affected by the bandwidth of a transmitter or a receiver. Therefore, in this paper, we investigate the effect of bandwidth on the chromatic dispersion monitoring of CSRZ signal based on clock-frequency component. As a result, we propose a couple of robust clock-extraction methods to monitor chromatic dispersion in CSRZ signal.

• The Journal of the Korea Contents Association
• /
• v.9 no.7
• /
• pp.76-85
• /
• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.10
• /
• pp.56-63
• /
• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.